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11/17/2022 06:42:15 AM
rwxr-xr-x
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Kbuild
599 bytes
01/28/2018 09:20:33 PM
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MC68328.h
37.82 KB
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MC68EZ328.h
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MC68VZ328.h
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a.out-core.h
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adb_iop.h
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amigahw.h
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amigaints.h
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amigayle.h
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amipcmcia.h
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apollohw.h
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asm-offsets.h
35 bytes
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asm-prototypes.h
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atafd.h
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atafdreg.h
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atari_joystick.h
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atari_stdma.h
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atari_stram.h
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atarihw.h
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atarikb.h
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atomic.h
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bitops.h
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blinken.h
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bootinfo.h
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bootstd.h
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bug.h
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bugs.h
369 bytes
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bvme6000hw.h
3.45 KB
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cache.h
296 bytes
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cacheflush.h
133 bytes
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cacheflush_mm.h
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cacheflush_no.h
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checksum.h
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cmpxchg.h
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coldfire.h
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contregs.h
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current.h
580 bytes
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delay.h
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div64.h
858 bytes
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dma-mapping.h
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dma.h
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dsp56k.h
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dvma.h
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elf.h
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entry.h
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export.h
74 bytes
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fb.h
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fbio.h
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flat.h
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floppy.h
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fpu.h
535 bytes
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ftrace.h
12 bytes
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gpio.h
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hardirq.h
594 bytes
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hash.h
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hp300hw.h
186 bytes
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hwtest.h
467 bytes
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ide.h
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idprom.h
725 bytes
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intersil.h
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io.h
383 bytes
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io_mm.h
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io_no.h
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irq.h
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irqflags.h
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kexec.h
732 bytes
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linkage.h
1.55 KB
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m5206sim.h
6.4 KB
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m520xsim.h
7.15 KB
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m523xsim.h
7.7 KB
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m525xsim.h
10.57 KB
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m5272sim.h
6.05 KB
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m527xsim.h
13.51 KB
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m528xsim.h
9.37 KB
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m52xxacr.h
3.57 KB
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m5307sim.h
7.52 KB
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m53xxacr.h
3.6 KB
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m53xxsim.h
53.97 KB
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m5407sim.h
6.14 KB
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m5441xsim.h
8.5 KB
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m54xxacr.h
4.82 KB
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m54xxgpt.h
3.66 KB
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m54xxpci.h
6.13 KB
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m54xxsim.h
3.8 KB
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mac_asc.h
520 bytes
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mac_baboon.h
999 bytes
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mac_iop.h
5.37 KB
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mac_oss.h
1.83 KB
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mac_psc.h
7.25 KB
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mac_via.h
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machdep.h
1.34 KB
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machines.h
3.13 KB
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machw.h
588 bytes
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macintosh.h
2.02 KB
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macints.h
3.28 KB
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math-emu.h
6.74 KB
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mc146818rtc.h
598 bytes
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mcf8390.h
3.75 KB
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mcf_pgalloc.h
2.37 KB
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mcf_pgtable.h
9.89 KB
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mcfclk.h
1.01 KB
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mcfdma.h
6.51 KB
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mcfgpio.h
8.48 KB
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mcfintc.h
3.09 KB
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mcfmmu.h
3.67 KB
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mcfpit.h
2.22 KB
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mcfqspi.h
1.82 KB
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mcfsim.h
1.5 KB
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mcfslt.h
1.21 KB
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mcftimer.h
2.3 KB
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mcfuart.h
6.91 KB
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mcfwdebug.h
4.99 KB
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mmu.h
243 bytes
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mmu_context.h
7.2 KB
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mmzone.h
264 bytes
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module.h
847 bytes
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motorola_pgalloc.h
2.26 KB
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motorola_pgtable.h
9.2 KB
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movs.h
1.44 KB
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mvme147hw.h
2.81 KB
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mvme16xhw.h
2.16 KB
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natfeat.h
533 bytes
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nettel.h
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nubus.h
1.21 KB
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openprom.h
7.98 KB
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oplib.h
9.54 KB
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page.h
1.47 KB
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page_mm.h
4.06 KB
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page_no.h
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page_offset.h
256 bytes
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parport.h
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pci.h
458 bytes
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pgalloc.h
444 bytes
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pgtable.h
127 bytes
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pgtable_mm.h
4.84 KB
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pgtable_no.h
1.57 KB
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processor.h
3.59 KB
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ptrace.h
643 bytes
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q40_master.h
2.28 KB
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q40ints.h
749 bytes
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quicc_simple.h
1.79 KB
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raw_io.h
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segment.h
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serial.h
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setup.h
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signal.h
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smp.h
32 bytes
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string.h
1.68 KB
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sun3-head.h
353 bytes
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sun3_pgalloc.h
2.26 KB
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sun3_pgtable.h
7.65 KB
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sun3ints.h
989 bytes
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sun3mmu.h
4.91 KB
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sun3x.h
868 bytes
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sun3xflop.h
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sun3xprom.h
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switch_to.h
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thread_info.h
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timex.h
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tlb.h
486 bytes
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tlbflush.h
5.95 KB
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traps.h
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uaccess.h
152 bytes
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uaccess_mm.h
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uaccess_no.h
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ucontext.h
570 bytes
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unaligned.h
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unistd.h
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user.h
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vga.h
651 bytes
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virtconvert.h
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zorro.h
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Editing: mcfdma.h
Close
/* SPDX-License-Identifier: GPL-2.0 */ /****************************************************************************/ /* * mcfdma.h -- Coldfire internal DMA support defines. * * (C) Copyright 1999, Rob Scott (rscott@mtrob.ml.org) */ /****************************************************************************/ #ifndef mcfdma_h #define mcfdma_h /****************************************************************************/ #if !defined(CONFIG_M5272) /* * Define the DMA register set addresses. * Note: these are longword registers, use unsigned long as data type */ #define MCFDMA_SAR 0x00 /* DMA source address (r/w) */ #define MCFDMA_DAR 0x01 /* DMA destination adr (r/w) */ /* these are word registers, use unsigned short data type */ #define MCFDMA_DCR 0x04 /* DMA control reg (r/w) */ #define MCFDMA_BCR 0x06 /* DMA byte count reg (r/w) */ /* these are byte registers, use unsiged char data type */ #define MCFDMA_DSR 0x10 /* DMA status reg (r/w) */ #define MCFDMA_DIVR 0x14 /* DMA interrupt vec (r/w) */ /* * Bit definitions for the DMA Control Register (DCR). */ #define MCFDMA_DCR_INT 0x8000 /* Enable completion irq */ #define MCFDMA_DCR_EEXT 0x4000 /* Enable external DMA req */ #define MCFDMA_DCR_CS 0x2000 /* Enable cycle steal */ #define MCFDMA_DCR_AA 0x1000 /* Enable auto alignment */ #define MCFDMA_DCR_BWC_MASK 0x0E00 /* Bandwidth ctl mask */ #define MCFDMA_DCR_BWC_512 0x0200 /* Bandwidth: 512 Bytes */ #define MCFDMA_DCR_BWC_1024 0x0400 /* Bandwidth: 1024 Bytes */ #define MCFDMA_DCR_BWC_2048 0x0600 /* Bandwidth: 2048 Bytes */ #define MCFDMA_DCR_BWC_4096 0x0800 /* Bandwidth: 4096 Bytes */ #define MCFDMA_DCR_BWC_8192 0x0a00 /* Bandwidth: 8192 Bytes */ #define MCFDMA_DCR_BWC_16384 0x0c00 /* Bandwidth: 16384 Bytes */ #define MCFDMA_DCR_BWC_32768 0x0e00 /* Bandwidth: 32768 Bytes */ #define MCFDMA_DCR_SAA 0x0100 /* Single Address Access */ #define MCFDMA_DCR_S_RW 0x0080 /* SAA read/write value */ #define MCFDMA_DCR_SINC 0x0040 /* Source addr inc enable */ #define MCFDMA_DCR_SSIZE_MASK 0x0030 /* Src xfer size */ #define MCFDMA_DCR_SSIZE_LONG 0x0000 /* Src xfer size, 00 = longw */ #define MCFDMA_DCR_SSIZE_BYTE 0x0010 /* Src xfer size, 01 = byte */ #define MCFDMA_DCR_SSIZE_WORD 0x0020 /* Src xfer size, 10 = word */ #define MCFDMA_DCR_SSIZE_LINE 0x0030 /* Src xfer size, 11 = line */ #define MCFDMA_DCR_DINC 0x0008 /* Dest addr inc enable */ #define MCFDMA_DCR_DSIZE_MASK 0x0006 /* Dest xfer size */ #define MCFDMA_DCR_DSIZE_LONG 0x0000 /* Dest xfer size, 00 = long */ #define MCFDMA_DCR_DSIZE_BYTE 0x0002 /* Dest xfer size, 01 = byte */ #define MCFDMA_DCR_DSIZE_WORD 0x0004 /* Dest xfer size, 10 = word */ #define MCFDMA_DCR_DSIZE_LINE 0x0006 /* Dest xfer size, 11 = line */ #define MCFDMA_DCR_START 0x0001 /* Start transfer */ /* * Bit definitions for the DMA Status Register (DSR). */ #define MCFDMA_DSR_CE 0x40 /* Config error */ #define MCFDMA_DSR_BES 0x20 /* Bus Error on source */ #define MCFDMA_DSR_BED 0x10 /* Bus Error on dest */ #define MCFDMA_DSR_REQ 0x04 /* Requests remaining */ #define MCFDMA_DSR_BSY 0x02 /* Busy */ #define MCFDMA_DSR_DONE 0x01 /* DMA transfer complete */ #else /* This is an MCF5272 */ #define MCFDMA_DMR 0x00 /* Mode Register (r/w) */ #define MCFDMA_DIR 0x03 /* Interrupt trigger register (r/w) */ #define MCFDMA_DSAR 0x03 /* Source Address register (r/w) */ #define MCFDMA_DDAR 0x04 /* Destination Address register (r/w) */ #define MCFDMA_DBCR 0x02 /* Byte Count Register (r/w) */ /* Bit definitions for the DMA Mode Register (DMR) */ #define MCFDMA_DMR_RESET 0x80000000L /* Reset bit */ #define MCFDMA_DMR_EN 0x40000000L /* DMA enable */ #define MCFDMA_DMR_RQM 0x000C0000L /* Request Mode Mask */ #define MCFDMA_DMR_RQM_DUAL 0x000C0000L /* Dual address mode, the only valid mode */ #define MCFDMA_DMR_DSTM 0x00002000L /* Destination addressing mask */ #define MCFDMA_DMR_DSTM_SA 0x00000000L /* Destination uses static addressing */ #define MCFDMA_DMR_DSTM_IA 0x00002000L /* Destination uses incremental addressing */ #define MCFDMA_DMR_DSTT_UD 0x00000400L /* Destination is user data */ #define MCFDMA_DMR_DSTT_UC 0x00000800L /* Destination is user code */ #define MCFDMA_DMR_DSTT_SD 0x00001400L /* Destination is supervisor data */ #define MCFDMA_DMR_DSTT_SC 0x00001800L /* Destination is supervisor code */ #define MCFDMA_DMR_DSTS_OFF 0x8 /* offset to the destination size bits */ #define MCFDMA_DMR_DSTS_LONG 0x00000000L /* Long destination size */ #define MCFDMA_DMR_DSTS_BYTE 0x00000100L /* Byte destination size */ #define MCFDMA_DMR_DSTS_WORD 0x00000200L /* Word destination size */ #define MCFDMA_DMR_DSTS_LINE 0x00000300L /* Line destination size */ #define MCFDMA_DMR_SRCM 0x00000020L /* Source addressing mask */ #define MCFDMA_DMR_SRCM_SA 0x00000000L /* Source uses static addressing */ #define MCFDMA_DMR_SRCM_IA 0x00000020L /* Source uses incremental addressing */ #define MCFDMA_DMR_SRCT_UD 0x00000004L /* Source is user data */ #define MCFDMA_DMR_SRCT_UC 0x00000008L /* Source is user code */ #define MCFDMA_DMR_SRCT_SD 0x00000014L /* Source is supervisor data */ #define MCFDMA_DMR_SRCT_SC 0x00000018L /* Source is supervisor code */ #define MCFDMA_DMR_SRCS_OFF 0x0 /* Offset to the source size bits */ #define MCFDMA_DMR_SRCS_LONG 0x00000000L /* Long source size */ #define MCFDMA_DMR_SRCS_BYTE 0x00000001L /* Byte source size */ #define MCFDMA_DMR_SRCS_WORD 0x00000002L /* Word source size */ #define MCFDMA_DMR_SRCS_LINE 0x00000003L /* Line source size */ /* Bit definitions for the DMA interrupt register (DIR) */ #define MCFDMA_DIR_INVEN 0x1000 /* Invalid Combination interrupt enable */ #define MCFDMA_DIR_ASCEN 0x0800 /* Address Sequence Complete (Completion) interrupt enable */ #define MCFDMA_DIR_TEEN 0x0200 /* Transfer Error interrupt enable */ #define MCFDMA_DIR_TCEN 0x0100 /* Transfer Complete (a bus transfer, that is) interrupt enable */ #define MCFDMA_DIR_INV 0x0010 /* Invalid Combination */ #define MCFDMA_DIR_ASC 0x0008 /* Address Sequence Complete (DMA Completion) */ #define MCFDMA_DIR_TE 0x0002 /* Transfer Error */ #define MCFDMA_DIR_TC 0x0001 /* Transfer Complete */ #endif /* !defined(CONFIG_M5272) */ /****************************************************************************/ #endif /* mcfdma_h */