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linux-headers-4.15.0-197
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m68k
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11/17/2022 06:42:15 AM
rwxr-xr-x
📄
Kbuild
599 bytes
01/28/2018 09:20:33 PM
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MC68328.h
37.82 KB
01/28/2018 09:20:33 PM
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MC68EZ328.h
37.74 KB
01/28/2018 09:20:33 PM
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MC68VZ328.h
41.02 KB
01/28/2018 09:20:33 PM
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a.out-core.h
1.98 KB
01/28/2018 09:20:33 PM
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adb_iop.h
1.09 KB
01/28/2018 09:20:33 PM
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amigahw.h
10.49 KB
01/28/2018 09:20:33 PM
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amigaints.h
3.5 KB
01/28/2018 09:20:33 PM
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amigayle.h
3.19 KB
01/28/2018 09:20:33 PM
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amipcmcia.h
2.51 KB
01/28/2018 09:20:33 PM
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apollohw.h
2.35 KB
01/28/2018 09:20:33 PM
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📄
asm-offsets.h
35 bytes
01/28/2018 09:20:33 PM
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asm-prototypes.h
211 bytes
01/28/2018 09:20:33 PM
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atafd.h
300 bytes
01/28/2018 09:20:33 PM
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atafdreg.h
2.68 KB
01/28/2018 09:20:33 PM
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📄
atari_joystick.h
457 bytes
01/28/2018 09:20:33 PM
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atari_stdma.h
514 bytes
01/28/2018 09:20:33 PM
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atari_stram.h
528 bytes
01/28/2018 09:20:33 PM
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atarihw.h
20.3 KB
01/28/2018 09:20:33 PM
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atariints.h
5.56 KB
01/28/2018 09:20:33 PM
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atarikb.h
1.4 KB
01/28/2018 09:20:33 PM
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atomic.h
4.86 KB
01/28/2018 09:20:33 PM
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bitops.h
12.19 KB
01/28/2018 09:20:33 PM
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blinken.h
641 bytes
01/28/2018 09:20:33 PM
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bootinfo.h
783 bytes
01/28/2018 09:20:33 PM
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bootstd.h
4.64 KB
01/28/2018 09:20:33 PM
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bug.h
659 bytes
11/01/2022 04:52:05 PM
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📄
bugs.h
369 bytes
01/28/2018 09:20:33 PM
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bvme6000hw.h
3.45 KB
01/28/2018 09:20:33 PM
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📄
cache.h
296 bytes
01/28/2018 09:20:33 PM
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cacheflush.h
133 bytes
01/28/2018 09:20:33 PM
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cacheflush_mm.h
6.92 KB
01/28/2018 09:20:33 PM
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cacheflush_no.h
2.61 KB
01/28/2018 09:20:33 PM
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checksum.h
3.4 KB
01/28/2018 09:20:33 PM
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cmpxchg.h
3.34 KB
01/28/2018 09:20:33 PM
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coldfire.h
1.61 KB
01/28/2018 09:20:33 PM
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contregs.h
3.31 KB
01/28/2018 09:20:33 PM
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current.h
580 bytes
01/28/2018 09:20:33 PM
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delay.h
3.43 KB
01/28/2018 09:20:33 PM
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📄
div64.h
858 bytes
01/28/2018 09:20:33 PM
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dma-mapping.h
291 bytes
01/28/2018 09:20:33 PM
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dma.h
16.65 KB
01/28/2018 09:20:33 PM
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dsp56k.h
1.24 KB
01/28/2018 09:20:33 PM
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dvma.h
9.67 KB
01/28/2018 09:20:33 PM
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elf.h
3.07 KB
01/28/2018 09:20:33 PM
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entry.h
5.76 KB
01/28/2018 09:20:33 PM
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export.h
74 bytes
01/28/2018 09:20:33 PM
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fb.h
921 bytes
01/28/2018 09:20:33 PM
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fbio.h
9.87 KB
01/28/2018 09:20:33 PM
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flat.h
1.02 KB
01/28/2018 09:20:33 PM
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floppy.h
5.06 KB
01/28/2018 09:20:33 PM
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fpu.h
535 bytes
01/28/2018 09:20:33 PM
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ftrace.h
12 bytes
01/28/2018 09:20:33 PM
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gpio.h
2.64 KB
01/28/2018 09:20:33 PM
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hardirq.h
594 bytes
01/28/2018 09:20:33 PM
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hash.h
2.07 KB
01/28/2018 09:20:33 PM
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📄
hp300hw.h
186 bytes
01/28/2018 09:20:33 PM
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hwtest.h
467 bytes
01/28/2018 09:20:33 PM
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ide.h
1.67 KB
01/28/2018 09:20:33 PM
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idprom.h
725 bytes
01/28/2018 09:20:33 PM
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📄
intersil.h
1.11 KB
01/28/2018 09:20:33 PM
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io.h
383 bytes
01/28/2018 09:20:33 PM
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io_mm.h
16.19 KB
01/28/2018 09:20:33 PM
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io_no.h
5.26 KB
01/28/2018 09:20:33 PM
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irq.h
2.57 KB
01/28/2018 09:20:33 PM
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irqflags.h
1.61 KB
01/28/2018 09:20:33 PM
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📄
kexec.h
732 bytes
01/28/2018 09:20:33 PM
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📄
linkage.h
1.55 KB
01/28/2018 09:20:33 PM
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📄
m5206sim.h
6.4 KB
01/28/2018 09:20:33 PM
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📄
m520xsim.h
7.15 KB
01/28/2018 09:20:33 PM
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📄
m523xsim.h
7.7 KB
01/28/2018 09:20:33 PM
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📄
m525xsim.h
10.57 KB
01/28/2018 09:20:33 PM
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📄
m5272sim.h
6.05 KB
01/28/2018 09:20:33 PM
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📄
m527xsim.h
13.51 KB
01/28/2018 09:20:33 PM
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📄
m528xsim.h
9.37 KB
01/28/2018 09:20:33 PM
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📄
m52xxacr.h
3.57 KB
01/28/2018 09:20:33 PM
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📄
m5307sim.h
7.52 KB
01/28/2018 09:20:33 PM
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📄
m53xxacr.h
3.6 KB
11/01/2022 04:52:05 PM
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📄
m53xxsim.h
53.97 KB
01/28/2018 09:20:33 PM
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📄
m5407sim.h
6.14 KB
01/28/2018 09:20:33 PM
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📄
m5441xsim.h
8.5 KB
01/28/2018 09:20:33 PM
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📄
m54xxacr.h
4.82 KB
01/28/2018 09:20:33 PM
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m54xxgpt.h
3.66 KB
01/28/2018 09:20:33 PM
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m54xxpci.h
6.13 KB
01/28/2018 09:20:33 PM
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📄
m54xxsim.h
3.8 KB
01/28/2018 09:20:33 PM
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📄
mac_asc.h
520 bytes
01/28/2018 09:20:33 PM
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📄
mac_baboon.h
999 bytes
01/28/2018 09:20:33 PM
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📄
mac_iop.h
5.37 KB
01/28/2018 09:20:33 PM
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📄
mac_oss.h
1.83 KB
01/28/2018 09:20:33 PM
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📄
mac_psc.h
7.25 KB
01/28/2018 09:20:33 PM
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📄
mac_via.h
11.44 KB
11/01/2022 04:52:05 PM
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📄
machdep.h
1.34 KB
01/28/2018 09:20:33 PM
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📄
machines.h
3.13 KB
01/28/2018 09:20:33 PM
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📄
machw.h
588 bytes
01/28/2018 09:20:33 PM
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📄
macintosh.h
2.02 KB
01/28/2018 09:20:33 PM
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📄
macints.h
3.28 KB
01/28/2018 09:20:33 PM
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📄
math-emu.h
6.74 KB
01/28/2018 09:20:33 PM
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📄
mc146818rtc.h
598 bytes
01/28/2018 09:20:33 PM
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📄
mcf8390.h
3.75 KB
01/28/2018 09:20:33 PM
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📄
mcf_pgalloc.h
2.37 KB
11/01/2022 04:52:05 PM
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📄
mcf_pgtable.h
9.89 KB
01/28/2018 09:20:33 PM
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📄
mcfclk.h
1.01 KB
01/28/2018 09:20:33 PM
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📄
mcfdma.h
6.51 KB
01/28/2018 09:20:33 PM
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📄
mcfgpio.h
8.48 KB
01/28/2018 09:20:33 PM
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📄
mcfintc.h
3.09 KB
01/28/2018 09:20:33 PM
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📄
mcfmmu.h
3.67 KB
01/28/2018 09:20:33 PM
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📄
mcfpit.h
2.22 KB
01/28/2018 09:20:33 PM
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📄
mcfqspi.h
1.82 KB
01/28/2018 09:20:33 PM
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mcfsim.h
1.5 KB
01/28/2018 09:20:33 PM
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📄
mcfslt.h
1.21 KB
01/28/2018 09:20:33 PM
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mcftimer.h
2.3 KB
01/28/2018 09:20:33 PM
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mcfuart.h
6.91 KB
01/28/2018 09:20:33 PM
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mcfwdebug.h
4.99 KB
01/28/2018 09:20:33 PM
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📄
mmu.h
243 bytes
01/28/2018 09:20:33 PM
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📄
mmu_context.h
7.2 KB
01/28/2018 09:20:33 PM
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mmzone.h
264 bytes
01/28/2018 09:20:33 PM
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📄
module.h
847 bytes
01/28/2018 09:20:33 PM
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📄
motorola_pgalloc.h
2.26 KB
01/28/2018 09:20:33 PM
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motorola_pgtable.h
9.2 KB
01/28/2018 09:20:33 PM
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movs.h
1.44 KB
01/28/2018 09:20:33 PM
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mvme147hw.h
2.81 KB
01/28/2018 09:20:33 PM
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mvme16xhw.h
2.16 KB
01/28/2018 09:20:33 PM
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natfeat.h
533 bytes
01/28/2018 09:20:33 PM
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nettel.h
2.95 KB
01/28/2018 09:20:33 PM
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nubus.h
1.21 KB
01/28/2018 09:20:33 PM
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openprom.h
7.98 KB
01/28/2018 09:20:33 PM
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oplib.h
9.54 KB
01/28/2018 09:20:33 PM
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page.h
1.47 KB
01/28/2018 09:20:33 PM
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page_mm.h
4.06 KB
01/28/2018 09:20:33 PM
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page_no.h
1.28 KB
01/28/2018 09:20:33 PM
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page_offset.h
256 bytes
01/28/2018 09:20:33 PM
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parport.h
837 bytes
01/28/2018 09:20:33 PM
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pci.h
458 bytes
01/28/2018 09:20:33 PM
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📄
pgalloc.h
444 bytes
01/28/2018 09:20:33 PM
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pgtable.h
127 bytes
01/28/2018 09:20:33 PM
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📄
pgtable_mm.h
4.84 KB
11/01/2022 04:52:05 PM
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pgtable_no.h
1.57 KB
11/01/2022 04:52:05 PM
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📄
processor.h
3.59 KB
01/28/2018 09:20:33 PM
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ptrace.h
643 bytes
01/28/2018 09:20:33 PM
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📄
q40_master.h
2.28 KB
01/28/2018 09:20:33 PM
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q40ints.h
749 bytes
01/28/2018 09:20:33 PM
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quicc_simple.h
1.79 KB
01/28/2018 09:20:33 PM
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raw_io.h
11.41 KB
11/01/2022 04:52:05 PM
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segment.h
1.42 KB
01/28/2018 09:20:33 PM
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serial.h
1.14 KB
01/28/2018 09:20:33 PM
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setup.h
9.25 KB
01/28/2018 09:20:33 PM
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signal.h
1.34 KB
01/28/2018 09:20:33 PM
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smp.h
32 bytes
01/28/2018 09:20:33 PM
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string.h
1.68 KB
01/28/2018 09:20:33 PM
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📄
sun3-head.h
353 bytes
01/28/2018 09:20:33 PM
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sun3_pgalloc.h
2.26 KB
01/28/2018 09:20:33 PM
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sun3_pgtable.h
7.65 KB
01/28/2018 09:20:33 PM
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sun3ints.h
989 bytes
01/28/2018 09:20:33 PM
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📄
sun3mmu.h
4.91 KB
01/28/2018 09:20:33 PM
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sun3x.h
868 bytes
01/28/2018 09:20:33 PM
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sun3xflop.h
5.62 KB
01/28/2018 09:20:33 PM
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sun3xprom.h
1.31 KB
01/28/2018 09:20:33 PM
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switch_to.h
1.51 KB
01/28/2018 09:20:33 PM
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thread_info.h
2.02 KB
01/28/2018 09:20:33 PM
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timex.h
974 bytes
11/01/2022 04:52:05 PM
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tlb.h
486 bytes
01/28/2018 09:20:33 PM
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tlbflush.h
5.95 KB
01/28/2018 09:20:33 PM
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traps.h
8.33 KB
01/28/2018 09:20:33 PM
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uaccess.h
152 bytes
01/28/2018 09:20:33 PM
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uaccess_mm.h
10.31 KB
01/28/2018 09:20:33 PM
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uaccess_no.h
3.69 KB
01/28/2018 09:20:33 PM
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ucontext.h
570 bytes
01/28/2018 09:20:33 PM
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unaligned.h
600 bytes
01/28/2018 09:20:33 PM
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unistd.h
952 bytes
01/28/2018 09:20:33 PM
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user.h
3.78 KB
01/28/2018 09:20:33 PM
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vga.h
651 bytes
01/28/2018 09:20:33 PM
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virtconvert.h
947 bytes
01/28/2018 09:20:33 PM
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zorro.h
1.17 KB
01/28/2018 09:20:33 PM
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Editing: m54xxpci.h
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/****************************************************************************/ /* * m54xxpci.h -- ColdFire 547x and 548x PCI bus support * * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org> * * This file is subject to the terms and conditions of the GNU General Public * License. See the file COPYING in the main directory of this archive * for more details. */ /****************************************************************************/ #ifndef M54XXPCI_H #define M54XXPCI_H /****************************************************************************/ /* * The core set of PCI support registers are mapped into the MBAR region. */ #define PCIIDR (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */ #define PCISCR (CONFIG_MBAR + 0xb04) /* PCI status/command */ #define PCICCRIR (CONFIG_MBAR + 0xb08) /* PCI class/revision */ #define PCICR1 (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */ #define PCIBAR0 (CONFIG_MBAR + 0xb10) /* PCI base address 0 */ #define PCIBAR1 (CONFIG_MBAR + 0xb14) /* PCI base address 1 */ #define PCICCPR (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */ #define PCISID (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */ #define PCIERBAR (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */ #define PCICPR (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */ #define PCICR2 (CONFIG_MBAR + 0xb3c) /* PCI configuration 2 */ #define PCIGSCR (CONFIG_MBAR + 0xb60) /* Global status/control */ #define PCITBATR0 (CONFIG_MBAR + 0xb64) /* Target base translation 0 */ #define PCITBATR1 (CONFIG_MBAR + 0xb68) /* Target base translation 1 */ #define PCITCR (CONFIG_MBAR + 0xb6c) /* Target control */ #define PCIIW0BTAR (CONFIG_MBAR + 0xb70) /* Initiator window 0 */ #define PCIIW1BTAR (CONFIG_MBAR + 0xb74) /* Initiator window 1 */ #define PCIIW2BTAR (CONFIG_MBAR + 0xb78) /* Initiator window 2 */ #define PCIIWCR (CONFIG_MBAR + 0xb80) /* Initiator window config */ #define PCIICR (CONFIG_MBAR + 0xb84) /* Initiator control */ #define PCIISR (CONFIG_MBAR + 0xb88) /* Initiator status */ #define PCICAR (CONFIG_MBAR + 0xbf8) /* Configuration address */ #define PCITPSR (CONFIG_MBAR + 0x8400) /* TX packet size */ #define PCITSAR (CONFIG_MBAR + 0x8404) /* TX start address */ #define PCITTCR (CONFIG_MBAR + 0x8408) /* TX transaction control */ #define PCITER (CONFIG_MBAR + 0x840c) /* TX enables */ #define PCITNAR (CONFIG_MBAR + 0x8410) /* TX next address */ #define PCITLWR (CONFIG_MBAR + 0x8414) /* TX last word */ #define PCITDCR (CONFIG_MBAR + 0x8418) /* TX done counts */ #define PCITSR (CONFIG_MBAR + 0x841c) /* TX status */ #define PCITFDR (CONFIG_MBAR + 0x8440) /* TX FIFO data */ #define PCITFSR (CONFIG_MBAR + 0x8444) /* TX FIFO status */ #define PCITFCR (CONFIG_MBAR + 0x8448) /* TX FIFO control */ #define PCITFAR (CONFIG_MBAR + 0x844c) /* TX FIFO alarm */ #define PCITFRPR (CONFIG_MBAR + 0x8450) /* TX FIFO read pointer */ #define PCITFWPR (CONFIG_MBAR + 0x8454) /* TX FIFO write pointer */ #define PCIRPSR (CONFIG_MBAR + 0x8480) /* RX packet size */ #define PCIRSAR (CONFIG_MBAR + 0x8484) /* RX start address */ #define PCIRTCR (CONFIG_MBAR + 0x8488) /* RX transaction control */ #define PCIRER (CONFIG_MBAR + 0x848c) /* RX enables */ #define PCIRNAR (CONFIG_MBAR + 0x8490) /* RX next address */ #define PCIRDCR (CONFIG_MBAR + 0x8498) /* RX done counts */ #define PCIRSR (CONFIG_MBAR + 0x849c) /* RX status */ #define PCIRFDR (CONFIG_MBAR + 0x84c0) /* RX FIFO data */ #define PCIRFSR (CONFIG_MBAR + 0x84c4) /* RX FIFO status */ #define PCIRFCR (CONFIG_MBAR + 0x84c8) /* RX FIFO control */ #define PCIRFAR (CONFIG_MBAR + 0x84cc) /* RX FIFO alarm */ #define PCIRFRPR (CONFIG_MBAR + 0x84d0) /* RX FIFO read pointer */ #define PCIRFWPR (CONFIG_MBAR + 0x84d4) /* RX FIFO write pointer */ #define PACR (CONFIG_MBAR + 0xc00) /* PCI arbiter control */ #define PASR (CONFIG_MBAR + 0xc04) /* PCI arbiter status */ /* * Definitions for the Global status and control register. */ #define PCIGSCR_PE 0x20000000 /* Parity error detected */ #define PCIGSCR_SE 0x10000000 /* System error detected */ #define PCIGSCR_XCLKBIN 0x07000000 /* XLB2CLKIN mask */ #define PCIGSCR_PEE 0x00002000 /* Parity error intr enable */ #define PCIGSCR_SEE 0x00001000 /* System error intr enable */ #define PCIGSCR_RESET 0x00000001 /* Reset bit */ /* * Bit definitions for the PCICAR configuration address register. */ #define PCICAR_E 0x80000000 /* Enable config space */ #define PCICAR_BUSN 16 /* Move bus bits */ #define PCICAR_DEVFNN 8 /* Move devfn bits */ #define PCICAR_DWORDN 0 /* Move dword bits */ /* * The initiator windows hold the memory and IO mapping information. * This macro creates the register values from the desired addresses. */ #define WXBTAR(hostaddr, pciaddr, size) \ (((hostaddr) & 0xff000000) | \ ((((size) - 1) & 0xff000000) >> 8) | \ (((pciaddr) & 0xff000000) >> 16)) #define PCIIWCR_W0_MEM 0x00000000 /* Window 0 is memory */ #define PCIIWCR_W0_IO 0x08000000 /* Window 0 is IO */ #define PCIIWCR_W0_MRD 0x00000000 /* Window 0 memory read */ #define PCIIWCR_W0_MRDL 0x02000000 /* Window 0 memory read line */ #define PCIIWCR_W0_MRDM 0x04000000 /* Window 0 memory read mult */ #define PCIIWCR_W0_E 0x01000000 /* Window 0 enable */ #define PCIIWCR_W1_MEM 0x00000000 /* Window 0 is memory */ #define PCIIWCR_W1_IO 0x00080000 /* Window 0 is IO */ #define PCIIWCR_W1_MRD 0x00000000 /* Window 0 memory read */ #define PCIIWCR_W1_MRDL 0x00020000 /* Window 0 memory read line */ #define PCIIWCR_W1_MRDM 0x00040000 /* Window 0 memory read mult */ #define PCIIWCR_W1_E 0x00010000 /* Window 0 enable */ /* * Bit definitions for the PCIBATR registers. */ #define PCITBATR0_E 0x00000001 /* Enable window 0 */ #define PCITBATR1_E 0x00000001 /* Enable window 1 */ /* * PCI arbiter support definitions and macros. */ #define PACR_INTMPRI 0x00000001 #define PACR_EXTMPRI(x) (((x) & 0x1f) << 1) #define PACR_INTMINTE 0x00010000 #define PACR_EXTMINTE(x) (((x) & 0x1f) << 17) #define PACR_PKMD 0x40000000 #define PACR_DS 0x80000000 #define PCICR1_CL(x) ((x) & 0xf) /* Cacheline size field */ #define PCICR1_LT(x) (((x) & 0xff) << 8) /* Latency timer field */ /****************************************************************************/ #endif /* M54XXPCI_H */