OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:15 AM	rwxr-xr-x
📄 Kbuild	599 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 MC68328.h	37.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 MC68EZ328.h	37.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 MC68VZ328.h	41.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 a.out-core.h	1.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 adb_iop.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amigahw.h	10.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amigaints.h	3.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amigayle.h	3.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amipcmcia.h	2.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 apollohw.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	211 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atafd.h	300 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atafdreg.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atari_joystick.h	457 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atari_stdma.h	514 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atari_stram.h	528 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atarihw.h	20.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atariints.h	5.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atarikb.h	1.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	4.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	12.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 blinken.h	641 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bootinfo.h	783 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bootstd.h	4.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	659 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 bugs.h	369 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bvme6000hw.h	3.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	296 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	133 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush_mm.h	6.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush_no.h	2.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	3.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 coldfire.h	1.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 contregs.h	3.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	580 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	3.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 div64.h	858 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	291 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	16.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dsp56k.h	1.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dvma.h	9.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 entry.h	5.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 export.h	74 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	921 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fbio.h	9.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flat.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	5.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu.h	535 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	12 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 gpio.h	2.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	594 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hash.h	2.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hp300hw.h	186 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hwtest.h	467 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	1.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 idprom.h	725 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 intersil.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	383 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io_mm.h	16.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io_no.h	5.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	2.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	1.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	732 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	1.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m5206sim.h	6.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m520xsim.h	7.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m523xsim.h	7.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m525xsim.h	10.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m5272sim.h	6.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m527xsim.h	13.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m528xsim.h	9.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m52xxacr.h	3.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m5307sim.h	7.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m53xxacr.h	3.6 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 m53xxsim.h	53.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m5407sim.h	6.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m5441xsim.h	8.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m54xxacr.h	4.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m54xxgpt.h	3.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m54xxpci.h	6.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m54xxsim.h	3.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_asc.h	520 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_baboon.h	999 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_iop.h	5.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_oss.h	1.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_psc.h	7.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_via.h	11.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 machdep.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 machines.h	3.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 machw.h	588 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 macintosh.h	2.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 macints.h	3.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 math-emu.h	6.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc.h	598 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcf8390.h	3.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcf_pgalloc.h	2.37 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mcf_pgtable.h	9.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfclk.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfdma.h	6.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfgpio.h	8.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfintc.h	3.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfmmu.h	3.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfpit.h	2.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfqspi.h	1.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfsim.h	1.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfslt.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcftimer.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfuart.h	6.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfwdebug.h	4.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	243 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	7.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone.h	264 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	847 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 motorola_pgalloc.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 motorola_pgtable.h	9.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 movs.h	1.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mvme147hw.h	2.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mvme16xhw.h	2.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 natfeat.h	533 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 nettel.h	2.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nubus.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 openprom.h	7.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 oplib.h	9.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	1.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_mm.h	4.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_no.h	1.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_offset.h	256 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 parport.h	837 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	458 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	444 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	127 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable_mm.h	4.84 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable_no.h	1.57 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 processor.h	3.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	643 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 q40_master.h	2.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 q40ints.h	749 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 quicc_simple.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 raw_io.h	11.41 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 segment.h	1.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	1.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	9.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	32 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3-head.h	353 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3_pgalloc.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3_pgtable.h	7.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3ints.h	989 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3mmu.h	4.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3x.h	868 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3xflop.h	5.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3xprom.h	1.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	1.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	2.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	974 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 tlb.h	486 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	5.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	8.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	152 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess_mm.h	10.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess_no.h	3.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ucontext.h	570 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	600 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	952 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	3.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	651 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 virtconvert.h	947 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 zorro.h	1.17 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: mac_psc.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Apple Peripheral System Controller (PSC)
 *
 * The PSC is used on the AV Macs to control IO functions not handled
 * by the VIAs (Ethernet, DSP, SCC, Sound). This includes nine DMA
 * channels.
 *
 * The first seven DMA channels appear to be "one-shot" and are actually
 * sets of two channels; one member is active while the other is being
 * configured, and then you flip the active member and start all over again.
 * The one-shot channels are grouped together and are:
 *
 * 1. SCSI
 * 2. Ethernet Read
 * 3. Ethernet Write
 * 4. Floppy Disk Controller
 * 5. SCC Channel A Receive
 * 6. SCC Channel B Receive
 * 7. SCC Channel A Transmit
 *
 * The remaining two channels are handled somewhat differently. They appear
 * to be closely tied and share one set of registers. They also seem to run
 * continuously, although how you keep the buffer filled in this scenario is
 * not understood as there seems to be only one input and one output buffer
 * pointer.
 *
 * Much of this was extrapolated from what was known about the Ethernet
 * registers and subsequently confirmed using MacsBug (ie by pinging the
 * machine with easy-to-find patterns and looking for them in the DMA
 * buffers, or by sending a file over the serial ports and finding the
 * file in the buffers.)
 *
 * 1999-05-25 (jmt)
 */

#define PSC_BASE	(0x50F31000)

/*
 * The IER/IFR registers work like the VIA, except that it has 4
 * of them each on different interrupt levels, and each register
 * set only seems to handle four interrupts instead of seven.
 *
 * To access a particular set of registers, add 0xn0 to the base
 * where n = 3,4,5 or 6.
 */

#define pIFRbase	0x100
#define pIERbase	0x104

/*
 * One-shot DMA control registers
 */

#define PSC_MYSTERY	0x804

#define PSC_CTL_BASE	0xC00

#define PSC_SCSI_CTL	0xC00
#define PSC_ENETRD_CTL  0xC10
#define PSC_ENETWR_CTL  0xC20
#define PSC_FDC_CTL	0xC30
#define PSC_SCCA_CTL	0xC40
#define PSC_SCCB_CTL	0xC50
#define PSC_SCCATX_CTL	0xC60

/*
 * DMA channels. Add +0x10 for the second channel in the set.
 * You're supposed to use one channel while the other runs and
 * then flip channels and do the whole thing again.
 */

#define PSC_ADDR_BASE	0x1000
#define PSC_LEN_BASE	0x1004
#define PSC_CMD_BASE	0x1008

#define PSC_SET0	0x00
#define PSC_SET1	0x10

#define PSC_SCSI_ADDR	0x1000	/* confirmed */
#define PSC_SCSI_LEN	0x1004	/* confirmed */
#define PSC_SCSI_CMD	0x1008	/* confirmed */
#define PSC_ENETRD_ADDR 0x1020	/* confirmed */
#define PSC_ENETRD_LEN  0x1024	/* confirmed */
#define PSC_ENETRD_CMD  0x1028	/* confirmed */
#define PSC_ENETWR_ADDR 0x1040	/* confirmed */
#define PSC_ENETWR_LEN  0x1044	/* confirmed */
#define PSC_ENETWR_CMD  0x1048	/* confirmed */
#define PSC_FDC_ADDR	0x1060	/* strongly suspected */
#define PSC_FDC_LEN	0x1064	/* strongly suspected */
#define PSC_FDC_CMD	0x1068	/* strongly suspected */
#define PSC_SCCA_ADDR	0x1080	/* confirmed */
#define PSC_SCCA_LEN	0x1084	/* confirmed */
#define PSC_SCCA_CMD	0x1088	/* confirmed */
#define PSC_SCCB_ADDR	0x10A0	/* confirmed */
#define PSC_SCCB_LEN	0x10A4	/* confirmed */
#define PSC_SCCB_CMD	0x10A8	/* confirmed */
#define PSC_SCCATX_ADDR	0x10C0	/* confirmed */
#define PSC_SCCATX_LEN	0x10C4	/* confirmed */
#define PSC_SCCATX_CMD	0x10C8	/* confirmed */

/*
 * Free-running DMA registers. The only part known for sure are the bits in
 * the control register, the buffer addresses and the buffer length. Everything
 * else is anybody's guess.
 *
 * These registers seem to be mirrored every thirty-two bytes up until offset
 * 0x300. It's safe to assume then that a new set of registers starts there.
 */

#define PSC_SND_CTL	0x200	/*
				 * [ 16-bit ]
				 * Sound (Singer?) control register.
				 *
				 * bit 0  : ????
				 * bit 1  : ????
				 * bit 2  : Set to one to enable sound
				 *          output. Possibly a mute flag.
				 * bit 3  : ????
				 * bit 4  : ????
				 * bit 5  : ????
				 * bit 6  : Set to one to enable pass-thru
				 *          audio. In this mode the audio data
				 *          seems to appear in both the input
				 *          buffer and the output buffer.
				 * bit 7  : Set to one to activate the
				 *          sound input DMA or zero to
				 *          disable it.
				 * bit 8  : Set to one to activate the
				 *          sound output DMA or zero to
				 *          disable it.
				 * bit 9  : \
				 * bit 11 :  |
				 *          These two bits control the sample
				 *          rate. Usually set to binary 10 and
				 *	    MacOS 8.0 says I'm at 48 KHz. Using
				 *	    a binary value of 01 makes things
				 *	    sound about 1/2 speed (24 KHz?) and
				 *          binary 00 is slower still (22 KHz?)
				 *
				 * Setting this to 0x0000 is a good way to
				 * kill all DMA at boot time so that the
				 * PSC won't overwrite the kernel image
				 * with sound data.
				 */

/*
 * 0x0202 - 0x0203 is unused. Writing there
 * seems to clobber the control register.
 */

#define PSC_SND_SOURCE	0x204	/*
				 * [ 32-bit ]
				 * Controls input source and volume:
				 *
				 * bits 12-15 : input source volume, 0 - F
				 * bits 16-19 : unknown, always 0x5
				 * bits 20-23 : input source selection:
				 *                  0x3 = CD Audio
				 *                  0x4 = External Audio
				 *
				 * The volume is definitely not the general
				 * output volume as it doesn't affect the
				 * alert sound volume.
				 */
#define PSC_SND_STATUS1	0x208	/*
				 * [ 32-bit ]
				 * Appears to be a read-only status register.
				 * The usual value is 0x00400002.
				 */
#define PSC_SND_HUH3	0x20C	/*
				 * [ 16-bit ]
				 * Unknown 16-bit value, always 0x0000.
				 */
#define PSC_SND_BITS2GO	0x20E	/*
				 * [ 16-bit ]
				 * Counts down to zero from some constant
				 * value. The value appears to be the
				 * number of _bits_ remaining before the
				 * buffer is full, which would make sense
				 * since Apple's docs say the sound DMA
				 * channels are 1 bit wide.
				 */
#define PSC_SND_INADDR	0x210	/*
				 * [ 32-bit ]
				 * Address of the sound input DMA buffer
				 */
#define PSC_SND_OUTADDR	0x214	/*
				 * [ 32-bit ]
				 * Address of the sound output DMA buffer
				 */
#define PSC_SND_LEN	0x218	/*
				 * [ 16-bit ]
				 * Length of both buffers in eight-byte units.
				 */
#define PSC_SND_HUH4	0x21A	/*
				 * [ 16-bit ]
				 * Unknown, always 0x0000.
				 */
#define PSC_SND_STATUS2	0x21C	/*
				 * [ 16-bit ]
				 * Appears to e a read-only status register.
				 * The usual value is 0x0200.
				 */
#define PSC_SND_HUH5	0x21E	/*
				 * [ 16-bit ]
				 * Unknown, always 0x0000.
				 */

#ifndef __ASSEMBLY__

extern volatile __u8 *psc;

extern void psc_register_interrupts(void);
extern void psc_irq_enable(int);
extern void psc_irq_disable(int);

/*
 *	Access functions
 */

static inline void psc_write_byte(int offset, __u8 data)
{
	*((volatile __u8 *)(psc + offset)) = data;
}

static inline void psc_write_word(int offset, __u16 data)
{
	*((volatile __u16 *)(psc + offset)) = data;
}

static inline void psc_write_long(int offset, __u32 data)
{
	*((volatile __u32 *)(psc + offset)) = data;
}

static inline u8 psc_read_byte(int offset)
{
	return *((volatile __u8 *)(psc + offset));
}

static inline u16 psc_read_word(int offset)
{
	return *((volatile __u16 *)(psc + offset));
}

static inline u32 psc_read_long(int offset)
{
	return *((volatile __u32 *)(psc + offset));
}

#endif /* __ASSEMBLY__ */