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11/17/2022 06:42:15 AM
rwxr-xr-x
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Kbuild
599 bytes
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MC68328.h
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MC68EZ328.h
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MC68VZ328.h
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a.out-core.h
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apollohw.h
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asm-offsets.h
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asm-prototypes.h
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atafd.h
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atafdreg.h
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atari_joystick.h
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atomic.h
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bitops.h
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blinken.h
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bootinfo.h
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bootstd.h
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bug.h
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bugs.h
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bvme6000hw.h
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cache.h
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cacheflush.h
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cacheflush_mm.h
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cacheflush_no.h
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checksum.h
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cmpxchg.h
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coldfire.h
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contregs.h
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current.h
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delay.h
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div64.h
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dma-mapping.h
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dma.h
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dsp56k.h
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dvma.h
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elf.h
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entry.h
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export.h
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fbio.h
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flat.h
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floppy.h
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fpu.h
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ftrace.h
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gpio.h
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hardirq.h
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hash.h
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hp300hw.h
186 bytes
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hwtest.h
467 bytes
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ide.h
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idprom.h
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intersil.h
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io.h
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io_mm.h
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io_no.h
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irq.h
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irqflags.h
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kexec.h
732 bytes
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linkage.h
1.55 KB
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m5206sim.h
6.4 KB
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m520xsim.h
7.15 KB
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m523xsim.h
7.7 KB
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m525xsim.h
10.57 KB
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m5272sim.h
6.05 KB
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m527xsim.h
13.51 KB
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m528xsim.h
9.37 KB
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m52xxacr.h
3.57 KB
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m5307sim.h
7.52 KB
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m53xxacr.h
3.6 KB
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m53xxsim.h
53.97 KB
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m5407sim.h
6.14 KB
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m5441xsim.h
8.5 KB
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m54xxacr.h
4.82 KB
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m54xxgpt.h
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m54xxpci.h
6.13 KB
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m54xxsim.h
3.8 KB
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mac_asc.h
520 bytes
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mac_baboon.h
999 bytes
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mac_iop.h
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mac_oss.h
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mac_psc.h
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mac_via.h
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machdep.h
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machines.h
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machw.h
588 bytes
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macintosh.h
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macints.h
3.28 KB
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math-emu.h
6.74 KB
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mc146818rtc.h
598 bytes
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mcf8390.h
3.75 KB
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mcf_pgalloc.h
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mcf_pgtable.h
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mcfclk.h
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mcfdma.h
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mcfgpio.h
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mcfintc.h
3.09 KB
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mcfmmu.h
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mcfpit.h
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mcfqspi.h
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mcfsim.h
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mcfslt.h
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mcftimer.h
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mcfuart.h
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mcfwdebug.h
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mmu.h
243 bytes
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mmu_context.h
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mmzone.h
264 bytes
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module.h
847 bytes
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motorola_pgalloc.h
2.26 KB
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motorola_pgtable.h
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movs.h
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mvme147hw.h
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mvme16xhw.h
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natfeat.h
533 bytes
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nettel.h
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nubus.h
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openprom.h
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oplib.h
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page.h
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page_mm.h
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page_no.h
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page_offset.h
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parport.h
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pci.h
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pgalloc.h
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pgtable.h
127 bytes
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pgtable_mm.h
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pgtable_no.h
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processor.h
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ptrace.h
643 bytes
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q40_master.h
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q40ints.h
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quicc_simple.h
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raw_io.h
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segment.h
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serial.h
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setup.h
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signal.h
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smp.h
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string.h
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sun3-head.h
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sun3_pgalloc.h
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sun3_pgtable.h
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sun3ints.h
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sun3mmu.h
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sun3x.h
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sun3xflop.h
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sun3xprom.h
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switch_to.h
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thread_info.h
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timex.h
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tlb.h
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tlbflush.h
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traps.h
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uaccess.h
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uaccess_mm.h
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uaccess_no.h
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ucontext.h
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unaligned.h
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unistd.h
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user.h
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vga.h
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virtconvert.h
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zorro.h
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Editing: m52xxacr.h
Close
/* SPDX-License-Identifier: GPL-2.0 */ /****************************************************************************/ /* * m52xxacr.h -- ColdFire version 2 core cache support * * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com> */ /****************************************************************************/ #ifndef m52xxacr_h #define m52xxacr_h /****************************************************************************/ /* * All varients of the ColdFire using version 2 cores have a similar * cache setup. Although not absolutely identical the cache register * definitions are compatible for all of them. Mostly they support a * configurable cache memory that can be instruction only, data only, * or split instruction and data. The exception is the very old version 2 * core based parts, like the 5206(e), 5249 and 5272, which are instruction * cache only. Cache size varies from 2k up to 16k. */ /* * Define the Cache Control register flags. */ #define CACR_CENB 0x80000000 /* Enable cache */ #define CACR_CDPI 0x10000000 /* Disable invalidation by CPUSHL */ #define CACR_CFRZ 0x08000000 /* Cache freeze mode */ #define CACR_CINV 0x01000000 /* Invalidate cache */ #define CACR_DISI 0x00800000 /* Disable instruction cache */ #define CACR_DISD 0x00400000 /* Disable data cache */ #define CACR_INVI 0x00200000 /* Invalidate instruction cache */ #define CACR_INVD 0x00100000 /* Invalidate data cache */ #define CACR_CEIB 0x00000400 /* Non-cachable instruction burst */ #define CACR_DCM 0x00000200 /* Default cache mode */ #define CACR_DBWE 0x00000100 /* Buffered write enable */ #define CACR_DWP 0x00000020 /* Write protection */ #define CACR_EUSP 0x00000010 /* Enable separate user a7 */ /* * Define the Access Control register flags. */ #define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */ #define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */ #define ACR_ENABLE 0x00008000 /* Enable this ACR */ #define ACR_USER 0x00000000 /* Allow only user accesses */ #define ACR_SUPER 0x00002000 /* Allow supervisor access only */ #define ACR_ANY 0x00004000 /* Allow any access type */ #define ACR_CENB 0x00000000 /* Caching of region enabled */ #define ACR_CDIS 0x00000040 /* Caching of region disabled */ #define ACR_BWE 0x00000020 /* Write buffer enabled */ #define ACR_WPROTECT 0x00000004 /* Write protect region */ /* * Set the cache controller settings we will use. On the cores that support * a split cache configuration we allow all the combinations at Kconfig * time. For those cores that only have an instruction cache we just set * that as on. */ #if defined(CONFIG_CACHE_I) #define CACHE_TYPE (CACR_DISD + CACR_EUSP) #define CACHE_INVTYPEI 0 #elif defined(CONFIG_CACHE_D) #define CACHE_TYPE (CACR_DISI + CACR_EUSP) #define CACHE_INVTYPED 0 #elif defined(CONFIG_CACHE_BOTH) #define CACHE_TYPE CACR_EUSP #define CACHE_INVTYPEI CACR_INVI #define CACHE_INVTYPED CACR_INVD #else /* This is the instruction cache only devices (no split cache, no eusp) */ #define CACHE_TYPE 0 #define CACHE_INVTYPEI 0 #endif #define CACHE_INIT (CACR_CINV + CACHE_TYPE) #define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM) #define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV) #if defined(CACHE_INVTYPEI) #define CACHE_INVALIDATEI (CACHE_MODE + CACR_CINV + CACHE_INVTYPEI) #endif #if defined(CACHE_INVTYPED) #define CACHE_INVALIDATED (CACHE_MODE + CACR_CINV + CACHE_INVTYPED) #endif #define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ (0x000f0000) + \ (ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE)) #define ACR1_MODE 0 /****************************************************************************/ #endif /* m52xxsim_h */