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linux-headers-4.15.0-197
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m68k
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asm
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11/17/2022 06:42:15 AM
rwxr-xr-x
📄
Kbuild
599 bytes
01/28/2018 09:20:33 PM
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MC68328.h
37.82 KB
01/28/2018 09:20:33 PM
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MC68EZ328.h
37.74 KB
01/28/2018 09:20:33 PM
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MC68VZ328.h
41.02 KB
01/28/2018 09:20:33 PM
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a.out-core.h
1.98 KB
01/28/2018 09:20:33 PM
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adb_iop.h
1.09 KB
01/28/2018 09:20:33 PM
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amigahw.h
10.49 KB
01/28/2018 09:20:33 PM
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amigaints.h
3.5 KB
01/28/2018 09:20:33 PM
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amigayle.h
3.19 KB
01/28/2018 09:20:33 PM
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amipcmcia.h
2.51 KB
01/28/2018 09:20:33 PM
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📄
apollohw.h
2.35 KB
01/28/2018 09:20:33 PM
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📄
asm-offsets.h
35 bytes
01/28/2018 09:20:33 PM
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asm-prototypes.h
211 bytes
01/28/2018 09:20:33 PM
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atafd.h
300 bytes
01/28/2018 09:20:33 PM
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atafdreg.h
2.68 KB
01/28/2018 09:20:33 PM
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📄
atari_joystick.h
457 bytes
01/28/2018 09:20:33 PM
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atari_stdma.h
514 bytes
01/28/2018 09:20:33 PM
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📄
atari_stram.h
528 bytes
01/28/2018 09:20:33 PM
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atarihw.h
20.3 KB
01/28/2018 09:20:33 PM
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atariints.h
5.56 KB
01/28/2018 09:20:33 PM
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atarikb.h
1.4 KB
01/28/2018 09:20:33 PM
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atomic.h
4.86 KB
01/28/2018 09:20:33 PM
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bitops.h
12.19 KB
01/28/2018 09:20:33 PM
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blinken.h
641 bytes
01/28/2018 09:20:33 PM
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bootinfo.h
783 bytes
01/28/2018 09:20:33 PM
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bootstd.h
4.64 KB
01/28/2018 09:20:33 PM
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bug.h
659 bytes
11/01/2022 04:52:05 PM
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📄
bugs.h
369 bytes
01/28/2018 09:20:33 PM
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📄
bvme6000hw.h
3.45 KB
01/28/2018 09:20:33 PM
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📄
cache.h
296 bytes
01/28/2018 09:20:33 PM
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cacheflush.h
133 bytes
01/28/2018 09:20:33 PM
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📄
cacheflush_mm.h
6.92 KB
01/28/2018 09:20:33 PM
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cacheflush_no.h
2.61 KB
01/28/2018 09:20:33 PM
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📄
checksum.h
3.4 KB
01/28/2018 09:20:33 PM
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cmpxchg.h
3.34 KB
01/28/2018 09:20:33 PM
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coldfire.h
1.61 KB
01/28/2018 09:20:33 PM
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contregs.h
3.31 KB
01/28/2018 09:20:33 PM
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current.h
580 bytes
01/28/2018 09:20:33 PM
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delay.h
3.43 KB
01/28/2018 09:20:33 PM
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📄
div64.h
858 bytes
01/28/2018 09:20:33 PM
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dma-mapping.h
291 bytes
01/28/2018 09:20:33 PM
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dma.h
16.65 KB
01/28/2018 09:20:33 PM
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dsp56k.h
1.24 KB
01/28/2018 09:20:33 PM
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dvma.h
9.67 KB
01/28/2018 09:20:33 PM
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elf.h
3.07 KB
01/28/2018 09:20:33 PM
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entry.h
5.76 KB
01/28/2018 09:20:33 PM
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export.h
74 bytes
01/28/2018 09:20:33 PM
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fb.h
921 bytes
01/28/2018 09:20:33 PM
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fbio.h
9.87 KB
01/28/2018 09:20:33 PM
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flat.h
1.02 KB
01/28/2018 09:20:33 PM
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floppy.h
5.06 KB
01/28/2018 09:20:33 PM
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fpu.h
535 bytes
01/28/2018 09:20:33 PM
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ftrace.h
12 bytes
01/28/2018 09:20:33 PM
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gpio.h
2.64 KB
01/28/2018 09:20:33 PM
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hardirq.h
594 bytes
01/28/2018 09:20:33 PM
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hash.h
2.07 KB
01/28/2018 09:20:33 PM
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📄
hp300hw.h
186 bytes
01/28/2018 09:20:33 PM
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📄
hwtest.h
467 bytes
01/28/2018 09:20:33 PM
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ide.h
1.67 KB
01/28/2018 09:20:33 PM
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📄
idprom.h
725 bytes
01/28/2018 09:20:33 PM
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📄
intersil.h
1.11 KB
01/28/2018 09:20:33 PM
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io.h
383 bytes
01/28/2018 09:20:33 PM
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📄
io_mm.h
16.19 KB
01/28/2018 09:20:33 PM
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io_no.h
5.26 KB
01/28/2018 09:20:33 PM
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irq.h
2.57 KB
01/28/2018 09:20:33 PM
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📄
irqflags.h
1.61 KB
01/28/2018 09:20:33 PM
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📄
kexec.h
732 bytes
01/28/2018 09:20:33 PM
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📄
linkage.h
1.55 KB
01/28/2018 09:20:33 PM
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📄
m5206sim.h
6.4 KB
01/28/2018 09:20:33 PM
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📄
m520xsim.h
7.15 KB
01/28/2018 09:20:33 PM
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📄
m523xsim.h
7.7 KB
01/28/2018 09:20:33 PM
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📄
m525xsim.h
10.57 KB
01/28/2018 09:20:33 PM
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📄
m5272sim.h
6.05 KB
01/28/2018 09:20:33 PM
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📄
m527xsim.h
13.51 KB
01/28/2018 09:20:33 PM
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📄
m528xsim.h
9.37 KB
01/28/2018 09:20:33 PM
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📄
m52xxacr.h
3.57 KB
01/28/2018 09:20:33 PM
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📄
m5307sim.h
7.52 KB
01/28/2018 09:20:33 PM
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📄
m53xxacr.h
3.6 KB
11/01/2022 04:52:05 PM
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📄
m53xxsim.h
53.97 KB
01/28/2018 09:20:33 PM
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📄
m5407sim.h
6.14 KB
01/28/2018 09:20:33 PM
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📄
m5441xsim.h
8.5 KB
01/28/2018 09:20:33 PM
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📄
m54xxacr.h
4.82 KB
01/28/2018 09:20:33 PM
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📄
m54xxgpt.h
3.66 KB
01/28/2018 09:20:33 PM
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📄
m54xxpci.h
6.13 KB
01/28/2018 09:20:33 PM
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📄
m54xxsim.h
3.8 KB
01/28/2018 09:20:33 PM
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📄
mac_asc.h
520 bytes
01/28/2018 09:20:33 PM
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📄
mac_baboon.h
999 bytes
01/28/2018 09:20:33 PM
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📄
mac_iop.h
5.37 KB
01/28/2018 09:20:33 PM
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📄
mac_oss.h
1.83 KB
01/28/2018 09:20:33 PM
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📄
mac_psc.h
7.25 KB
01/28/2018 09:20:33 PM
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📄
mac_via.h
11.44 KB
11/01/2022 04:52:05 PM
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📄
machdep.h
1.34 KB
01/28/2018 09:20:33 PM
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📄
machines.h
3.13 KB
01/28/2018 09:20:33 PM
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📄
machw.h
588 bytes
01/28/2018 09:20:33 PM
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📄
macintosh.h
2.02 KB
01/28/2018 09:20:33 PM
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📄
macints.h
3.28 KB
01/28/2018 09:20:33 PM
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📄
math-emu.h
6.74 KB
01/28/2018 09:20:33 PM
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📄
mc146818rtc.h
598 bytes
01/28/2018 09:20:33 PM
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📄
mcf8390.h
3.75 KB
01/28/2018 09:20:33 PM
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📄
mcf_pgalloc.h
2.37 KB
11/01/2022 04:52:05 PM
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📄
mcf_pgtable.h
9.89 KB
01/28/2018 09:20:33 PM
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📄
mcfclk.h
1.01 KB
01/28/2018 09:20:33 PM
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📄
mcfdma.h
6.51 KB
01/28/2018 09:20:33 PM
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📄
mcfgpio.h
8.48 KB
01/28/2018 09:20:33 PM
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📄
mcfintc.h
3.09 KB
01/28/2018 09:20:33 PM
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📄
mcfmmu.h
3.67 KB
01/28/2018 09:20:33 PM
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📄
mcfpit.h
2.22 KB
01/28/2018 09:20:33 PM
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📄
mcfqspi.h
1.82 KB
01/28/2018 09:20:33 PM
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mcfsim.h
1.5 KB
01/28/2018 09:20:33 PM
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📄
mcfslt.h
1.21 KB
01/28/2018 09:20:33 PM
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mcftimer.h
2.3 KB
01/28/2018 09:20:33 PM
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mcfuart.h
6.91 KB
01/28/2018 09:20:33 PM
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mcfwdebug.h
4.99 KB
01/28/2018 09:20:33 PM
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📄
mmu.h
243 bytes
01/28/2018 09:20:33 PM
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📄
mmu_context.h
7.2 KB
01/28/2018 09:20:33 PM
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mmzone.h
264 bytes
01/28/2018 09:20:33 PM
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📄
module.h
847 bytes
01/28/2018 09:20:33 PM
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📄
motorola_pgalloc.h
2.26 KB
01/28/2018 09:20:33 PM
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motorola_pgtable.h
9.2 KB
01/28/2018 09:20:33 PM
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📄
movs.h
1.44 KB
01/28/2018 09:20:33 PM
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📄
mvme147hw.h
2.81 KB
01/28/2018 09:20:33 PM
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mvme16xhw.h
2.16 KB
01/28/2018 09:20:33 PM
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natfeat.h
533 bytes
01/28/2018 09:20:33 PM
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nettel.h
2.95 KB
01/28/2018 09:20:33 PM
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nubus.h
1.21 KB
01/28/2018 09:20:33 PM
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openprom.h
7.98 KB
01/28/2018 09:20:33 PM
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oplib.h
9.54 KB
01/28/2018 09:20:33 PM
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page.h
1.47 KB
01/28/2018 09:20:33 PM
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page_mm.h
4.06 KB
01/28/2018 09:20:33 PM
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page_no.h
1.28 KB
01/28/2018 09:20:33 PM
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page_offset.h
256 bytes
01/28/2018 09:20:33 PM
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parport.h
837 bytes
01/28/2018 09:20:33 PM
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pci.h
458 bytes
01/28/2018 09:20:33 PM
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📄
pgalloc.h
444 bytes
01/28/2018 09:20:33 PM
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pgtable.h
127 bytes
01/28/2018 09:20:33 PM
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📄
pgtable_mm.h
4.84 KB
11/01/2022 04:52:05 PM
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pgtable_no.h
1.57 KB
11/01/2022 04:52:05 PM
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📄
processor.h
3.59 KB
01/28/2018 09:20:33 PM
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ptrace.h
643 bytes
01/28/2018 09:20:33 PM
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📄
q40_master.h
2.28 KB
01/28/2018 09:20:33 PM
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📄
q40ints.h
749 bytes
01/28/2018 09:20:33 PM
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📄
quicc_simple.h
1.79 KB
01/28/2018 09:20:33 PM
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raw_io.h
11.41 KB
11/01/2022 04:52:05 PM
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segment.h
1.42 KB
01/28/2018 09:20:33 PM
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serial.h
1.14 KB
01/28/2018 09:20:33 PM
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setup.h
9.25 KB
01/28/2018 09:20:33 PM
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signal.h
1.34 KB
01/28/2018 09:20:33 PM
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smp.h
32 bytes
01/28/2018 09:20:33 PM
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string.h
1.68 KB
01/28/2018 09:20:33 PM
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📄
sun3-head.h
353 bytes
01/28/2018 09:20:33 PM
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📄
sun3_pgalloc.h
2.26 KB
01/28/2018 09:20:33 PM
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sun3_pgtable.h
7.65 KB
01/28/2018 09:20:33 PM
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sun3ints.h
989 bytes
01/28/2018 09:20:33 PM
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📄
sun3mmu.h
4.91 KB
01/28/2018 09:20:33 PM
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sun3x.h
868 bytes
01/28/2018 09:20:33 PM
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sun3xflop.h
5.62 KB
01/28/2018 09:20:33 PM
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sun3xprom.h
1.31 KB
01/28/2018 09:20:33 PM
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switch_to.h
1.51 KB
01/28/2018 09:20:33 PM
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thread_info.h
2.02 KB
01/28/2018 09:20:33 PM
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timex.h
974 bytes
11/01/2022 04:52:05 PM
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tlb.h
486 bytes
01/28/2018 09:20:33 PM
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tlbflush.h
5.95 KB
01/28/2018 09:20:33 PM
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traps.h
8.33 KB
01/28/2018 09:20:33 PM
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uaccess.h
152 bytes
01/28/2018 09:20:33 PM
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uaccess_mm.h
10.31 KB
01/28/2018 09:20:33 PM
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uaccess_no.h
3.69 KB
01/28/2018 09:20:33 PM
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ucontext.h
570 bytes
01/28/2018 09:20:33 PM
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unaligned.h
600 bytes
01/28/2018 09:20:33 PM
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unistd.h
952 bytes
01/28/2018 09:20:33 PM
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user.h
3.78 KB
01/28/2018 09:20:33 PM
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vga.h
651 bytes
01/28/2018 09:20:33 PM
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virtconvert.h
947 bytes
01/28/2018 09:20:33 PM
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zorro.h
1.17 KB
01/28/2018 09:20:33 PM
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Editing: m54xxacr.h
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/* SPDX-License-Identifier: GPL-2.0 */ /* * Bit definitions for the MCF54xx ACR and CACR registers. */ #ifndef m54xxacr_h #define m54xxacr_h /* * Define the Cache register flags. */ #define CACR_DEC 0x80000000 /* Enable data cache */ #define CACR_DWP 0x40000000 /* Data write protection */ #define CACR_DESB 0x20000000 /* Enable data store buffer */ #define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */ #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ #define CACR_DDCM_WT 0x00000000 /* Write through cache*/ #define CACR_DDCM_CP 0x02000000 /* Copyback cache */ #define CACR_DDCM_P 0x04000000 /* No cache, precise */ #define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ #define CACR_DCINVA 0x01000000 /* Invalidate data cache */ #define CACR_BEC 0x00080000 /* Enable branch cache */ #define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ #define CACR_IEC 0x00008000 /* Enable instruction cache */ #define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ #define CACR_IDPI 0x00001000 /* Disable CPUSHL */ #define CACR_IHLCK 0x00000800 /* Instruction cache half lock */ #define CACR_IDCM 0x00000400 /* Instruction cache inhibit */ #define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ #define CACR_EUSP 0x00000020 /* Enable separate user a7 */ #define ACR_BASE_POS 24 /* Address Base */ #define ACR_MASK_POS 16 /* Address Mask */ #define ACR_ENABLE 0x00008000 /* Enable address */ #define ACR_USER 0x00000000 /* User mode access only */ #define ACR_SUPER 0x00002000 /* Supervisor mode only */ #define ACR_ANY 0x00004000 /* Match any access mode */ #define ACR_CM_WT 0x00000000 /* Write through mode */ #define ACR_CM_CP 0x00000020 /* Copyback mode */ #define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ #define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ #define ACR_CM 0x00000060 /* Cache mode mask */ #define ACR_SP 0x00000008 /* Supervisor protect */ #define ACR_WPROTECT 0x00000004 /* Write protect */ #define ACR_BA(x) ((x) & 0xff000000) #define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8) #if defined(CONFIG_M5407) #define ICACHE_SIZE 0x4000 /* instruction - 16k */ #define DCACHE_SIZE 0x2000 /* data - 8k */ #elif defined(CONFIG_M54xx) #define ICACHE_SIZE 0x8000 /* instruction - 32k */ #define DCACHE_SIZE 0x8000 /* data - 32k */ #elif defined(CONFIG_M5441x) #define ICACHE_SIZE 0x2000 /* instruction - 8k */ #define DCACHE_SIZE 0x2000 /* data - 8k */ #endif #define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ #define CACHE_WAYS 4 /* 4 ways */ #define ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS) #define DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS) #define ICACHE_MAX_ADDR ICACHE_SET_MASK #define DCACHE_MAX_ADDR DCACHE_SET_MASK /* * Version 4 cores have a true harvard style separate instruction * and data cache. Enable data and instruction caches, also enable write * buffers and branch accelerator. */ /* attention : enabling CACR_DESB requires a "nop" to flush the store buffer */ /* use '+' instead of '|' for assembler's sake */ /* Enable data cache */ /* Enable data store buffer */ /* outside ACRs : No cache, precise */ /* Enable instruction+branch caches */ #if defined(CONFIG_M5407) #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC) #else #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP) #endif #define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) #if defined(CONFIG_MMU) /* * If running with the MMU enabled then we need to map the internal * register region as non-cacheable. And then we map all our RAM as * cacheable and supervisor access only. */ #define ACR0_MODE (ACR_BA(IOMEMBASE)+ACR_ADMSK(IOMEMSIZE)+ \ ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP) #if defined(CONFIG_CACHE_COPYBACK) #define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP) #else #define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT) #endif #define ACR2_MODE 0 #define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ ACR_ENABLE+ACR_SUPER+ACR_SP) #else /* * For the non-MMU enabled case we map all of RAM as cacheable. */ #if defined(CONFIG_CACHE_COPYBACK) #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP) #else #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) #endif #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) #define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) #define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA) #define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA) #define ACR0_MODE (0x000f0000+DATA_CACHE_MODE) #define ACR1_MODE 0 #define ACR2_MODE (0x000f0000+INSN_CACHE_MODE) #define ACR3_MODE 0 #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP) /* Copyback cache mode must push dirty cache lines first */ #define CACHE_PUSH #endif #endif /* CONFIG_MMU */ #endif /* m54xxacr_h */