OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:12 AM	rwxr-xr-x
📄 Kbuild	703 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 acenv.h	541 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 acpi.h	4.34 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 alternative.h	7.63 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 arch_gicv3.h	3.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 arch_timer.h	4.87 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 arm-cci.h	794 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-bug.h	1.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-uaccess.h	2.09 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 assembler.h	13.51 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 atomic.h	8.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic_ll_sc.h	10.61 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 atomic_lse.h	14.82 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 barrier.h	3.78 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 bitops.h	1.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitrev.h	452 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 boot.h	384 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 brk-imm.h	706 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	2.23 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cacheflush.h	4.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	1.35 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 clocksource.h	192 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	7.98 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compat.h	7.15 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compiler.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu.h	1.84 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpu_ops.h	2.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpucaps.h	1.87 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpufeature.h	19.14 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpuidle.h	401 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cputype.h	8.1 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 current.h	517 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 daifflags.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcc.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 debug-monitors.h	3.76 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 device.h	886 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	2.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dmi.h	850 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 efi.h	4.57 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 elf.h	5.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 esr.h	9.02 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 exception.h	1.21 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 exec.h	868 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable.h	815 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	1000 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.91 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 fpsimd.h	4.21 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 fpsimdmacros.h	5.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	1.92 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 futex.h	3.41 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hardirq.h	2.08 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hugetlb.h	2.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_breakpoint.h	4.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hwcap.h	1.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hypervisor.h	144 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 insn.h	16.03 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 io.h	7.72 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 irq.h	307 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_work.h	228 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	1.68 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kasan.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kernel-pgtable.h	4.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	2.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	3.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	1.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_arm.h	8.38 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_asm.h	4.26 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_coproc.h	2.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_emulate.h	10.38 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_host.h	15.73 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_hyp.h	5.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_mmio.h	1.3 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_mmu.h	11.72 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 linkage.h	114 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 lse.h	1.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 memblock.h	720 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 memory.h	9.16 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmu.h	2.76 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmu_context.h	6.35 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmzone.h	266 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	2.8 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 neon.h	815 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 numa.h	1.33 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 page-def.h	1.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	1.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 paravirt.h	458 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	878 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu.h	7.48 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 perf_event.h	3.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	3.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-hwdef.h	9.4 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtable-prot.h	4.38 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtable-types.h	1.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	21.55 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 probes.h	1022 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 proc-fns.h	1.21 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 processor.h	6.52 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ptdump.h	1.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	9 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 sdei.h	1.46 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 seccomp.h	714 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	1.46 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 shmparam.h	965 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal32.h	1.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 simd.h	1.39 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 smp.h	4.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp_plat.h	1.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sparsemem.h	771 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	3.33 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 spinlock_types.h	1.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stack_pointer.h	247 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackprotector.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	2.53 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 stage2_pgtable-nopmd.h	1.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stage2_pgtable-nopud.h	1.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stage2_pgtable.h	4.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stat.h	1.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	2.33 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 suspend.h	1.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sync_bitops.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	2.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sysreg.h	25.1 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 system_misc.h	1.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	3.93 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 timex.h	883 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	2.22 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tlbflush.h	5.38 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 topology.h	1.29 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 traps.h	3.33 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 uaccess.h	12.01 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 unistd.h	1.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd32.h	27.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uprobes.h	777 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso_datapage.h	1.53 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 vectors.h	1.75 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 virt.h	3 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 vmap_stack.h	769 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 word-at-a-time.h	2.22 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 xen	-	05/09/2024 07:14:16 AM	rwxr-xr-x

Editing: pgtable-hwdef.h

/*
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_PGTABLE_HWDEF_H
#define __ASM_PGTABLE_HWDEF_H

/*
 * Number of page-table levels required to address 'va_bits' wide
 * address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT)
 * bits with (PAGE_SHIFT - 3) bits at each page table level. Hence:
 *
 *  levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3))
 *
 * where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d))
 *
 * We cannot include linux/kernel.h which defines DIV_ROUND_UP here
 * due to build issues. So we open code DIV_ROUND_UP here:
 *
 *	((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3))
 *
 * which gets simplified as :
 */
#define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3))

/*
 * Size mapped by an entry at level n ( 0 <= n <= 3)
 * We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits
 * in the final page. The maximum number of translation levels supported by
 * the architecture is 4. Hence, starting at at level n, we have further
 * ((4 - n) - 1) levels of translation excluding the offset within the page.
 * So, the total number of bits mapped by an entry at level n is :
 *
 *  ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT
 *
 * Rearranging it a bit we get :
 *   (4 - n) * (PAGE_SHIFT - 3) + 3
 */
#define ARM64_HW_PGTABLE_LEVEL_SHIFT(n)	((PAGE_SHIFT - 3) * (4 - (n)) + 3)

#define PTRS_PER_PTE		(1 << (PAGE_SHIFT - 3))

/*
 * PMD_SHIFT determines the size a level 2 page table entry can map.
 */
#if CONFIG_PGTABLE_LEVELS > 2
#define PMD_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(2)
#define PMD_SIZE		(_AC(1, UL) << PMD_SHIFT)
#define PMD_MASK		(~(PMD_SIZE-1))
#define PTRS_PER_PMD		PTRS_PER_PTE
#endif

/*
 * PUD_SHIFT determines the size a level 1 page table entry can map.
 */
#if CONFIG_PGTABLE_LEVELS > 3
#define PUD_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(1)
#define PUD_SIZE		(_AC(1, UL) << PUD_SHIFT)
#define PUD_MASK		(~(PUD_SIZE-1))
#define PTRS_PER_PUD		PTRS_PER_PTE
#endif

/*
 * PGDIR_SHIFT determines the size a top-level page table entry can map
 * (depending on the configuration, this level can be 0, 1 or 2).
 */
#define PGDIR_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS)
#define PGDIR_SIZE		(_AC(1, UL) << PGDIR_SHIFT)
#define PGDIR_MASK		(~(PGDIR_SIZE-1))
#define PTRS_PER_PGD		(1 << (VA_BITS - PGDIR_SHIFT))

/*
 * Section address mask and size definitions.
 */
#define SECTION_SHIFT		PMD_SHIFT
#define SECTION_SIZE		(_AC(1, UL) << SECTION_SHIFT)
#define SECTION_MASK		(~(SECTION_SIZE-1))

/*
 * Contiguous page definitions.
 */
#ifdef CONFIG_ARM64_64K_PAGES
#define CONT_PTE_SHIFT		5
#define CONT_PMD_SHIFT		5
#elif defined(CONFIG_ARM64_16K_PAGES)
#define CONT_PTE_SHIFT		7
#define CONT_PMD_SHIFT		5
#else
#define CONT_PTE_SHIFT		4
#define CONT_PMD_SHIFT		4
#endif

#define CONT_PTES		(1 << CONT_PTE_SHIFT)
#define CONT_PTE_SIZE		(CONT_PTES * PAGE_SIZE)
#define CONT_PTE_MASK		(~(CONT_PTE_SIZE - 1))
#define CONT_PMDS		(1 << CONT_PMD_SHIFT)
#define CONT_PMD_SIZE		(CONT_PMDS * PMD_SIZE)
#define CONT_PMD_MASK		(~(CONT_PMD_SIZE - 1))
/* the the numerical offset of the PTE within a range of CONT_PTES */
#define CONT_RANGE_OFFSET(addr) (((addr)>>PAGE_SHIFT)&(CONT_PTES-1))

/*
 * Hardware page table definitions.
 *
 * Level 1 descriptor (PUD).
 */
#define PUD_TYPE_TABLE		(_AT(pudval_t, 3) << 0)
#define PUD_TABLE_BIT		(_AT(pgdval_t, 1) << 1)
#define PUD_TYPE_MASK		(_AT(pgdval_t, 3) << 0)
#define PUD_TYPE_SECT		(_AT(pgdval_t, 1) << 0)

/*
 * Level 2 descriptor (PMD).
 */
#define PMD_TYPE_MASK		(_AT(pmdval_t, 3) << 0)
#define PMD_TYPE_FAULT		(_AT(pmdval_t, 0) << 0)
#define PMD_TYPE_TABLE		(_AT(pmdval_t, 3) << 0)
#define PMD_TYPE_SECT		(_AT(pmdval_t, 1) << 0)
#define PMD_TABLE_BIT		(_AT(pmdval_t, 1) << 1)

/*
 * Section
 */
#define PMD_SECT_VALID		(_AT(pmdval_t, 1) << 0)
#define PMD_SECT_USER		(_AT(pmdval_t, 1) << 6)		/* AP[1] */
#define PMD_SECT_RDONLY		(_AT(pmdval_t, 1) << 7)		/* AP[2] */
#define PMD_SECT_S		(_AT(pmdval_t, 3) << 8)
#define PMD_SECT_AF		(_AT(pmdval_t, 1) << 10)
#define PMD_SECT_NG		(_AT(pmdval_t, 1) << 11)
#define PMD_SECT_CONT		(_AT(pmdval_t, 1) << 52)
#define PMD_SECT_PXN		(_AT(pmdval_t, 1) << 53)
#define PMD_SECT_UXN		(_AT(pmdval_t, 1) << 54)

/*
 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
 */
#define PMD_ATTRINDX(t)		(_AT(pmdval_t, (t)) << 2)
#define PMD_ATTRINDX_MASK	(_AT(pmdval_t, 7) << 2)

/*
 * Level 3 descriptor (PTE).
 */
#define PTE_TYPE_MASK		(_AT(pteval_t, 3) << 0)
#define PTE_TYPE_FAULT		(_AT(pteval_t, 0) << 0)
#define PTE_TYPE_PAGE		(_AT(pteval_t, 3) << 0)
#define PTE_TABLE_BIT		(_AT(pteval_t, 1) << 1)
#define PTE_USER		(_AT(pteval_t, 1) << 6)		/* AP[1] */
#define PTE_RDONLY		(_AT(pteval_t, 1) << 7)		/* AP[2] */
#define PTE_SHARED		(_AT(pteval_t, 3) << 8)		/* SH[1:0], inner shareable */
#define PTE_AF			(_AT(pteval_t, 1) << 10)	/* Access Flag */
#define PTE_NG			(_AT(pteval_t, 1) << 11)	/* nG */
#define PTE_DBM			(_AT(pteval_t, 1) << 51)	/* Dirty Bit Management */
#define PTE_CONT		(_AT(pteval_t, 1) << 52)	/* Contiguous range */
#define PTE_PXN			(_AT(pteval_t, 1) << 53)	/* Privileged XN */
#define PTE_UXN			(_AT(pteval_t, 1) << 54)	/* User XN */
#define PTE_HYP_XN		(_AT(pteval_t, 1) << 54)	/* HYP XN */

/*
 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
 */
#define PTE_ATTRINDX(t)		(_AT(pteval_t, (t)) << 2)
#define PTE_ATTRINDX_MASK	(_AT(pteval_t, 7) << 2)

/*
 * 2nd stage PTE definitions
 */
#define PTE_S2_RDONLY		(_AT(pteval_t, 1) << 6)   /* HAP[2:1] */
#define PTE_S2_RDWR		(_AT(pteval_t, 3) << 6)   /* HAP[2:1] */

#define PMD_S2_RDONLY		(_AT(pmdval_t, 1) << 6)   /* HAP[2:1] */
#define PMD_S2_RDWR		(_AT(pmdval_t, 3) << 6)   /* HAP[2:1] */

/*
 * Memory Attribute override for Stage-2 (MemAttr[3:0])
 */
#define PTE_S2_MEMATTR(t)	(_AT(pteval_t, (t)) << 2)
#define PTE_S2_MEMATTR_MASK	(_AT(pteval_t, 0xf) << 2)

/*
 * EL2/HYP PTE/PMD definitions
 */
#define PMD_HYP			PMD_SECT_USER
#define PTE_HYP			PTE_USER

/*
 * Highest possible physical address supported.
 */
#define PHYS_MASK_SHIFT		(48)
#define PHYS_MASK		((UL(1) << PHYS_MASK_SHIFT) - 1)

/*
 * TCR flags.
 */
#define TCR_T0SZ_OFFSET		0
#define TCR_T1SZ_OFFSET		16
#define TCR_T0SZ(x)		((UL(64) - (x)) << TCR_T0SZ_OFFSET)
#define TCR_T1SZ(x)		((UL(64) - (x)) << TCR_T1SZ_OFFSET)
#define TCR_TxSZ(x)		(TCR_T0SZ(x) | TCR_T1SZ(x))
#define TCR_TxSZ_WIDTH		6
#define TCR_T0SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)

#define TCR_IRGN0_SHIFT		8
#define TCR_IRGN0_MASK		(UL(3) << TCR_IRGN0_SHIFT)
#define TCR_IRGN0_NC		(UL(0) << TCR_IRGN0_SHIFT)
#define TCR_IRGN0_WBWA		(UL(1) << TCR_IRGN0_SHIFT)
#define TCR_IRGN0_WT		(UL(2) << TCR_IRGN0_SHIFT)
#define TCR_IRGN0_WBnWA		(UL(3) << TCR_IRGN0_SHIFT)

#define TCR_IRGN1_SHIFT		24
#define TCR_IRGN1_MASK		(UL(3) << TCR_IRGN1_SHIFT)
#define TCR_IRGN1_NC		(UL(0) << TCR_IRGN1_SHIFT)
#define TCR_IRGN1_WBWA		(UL(1) << TCR_IRGN1_SHIFT)
#define TCR_IRGN1_WT		(UL(2) << TCR_IRGN1_SHIFT)
#define TCR_IRGN1_WBnWA		(UL(3) << TCR_IRGN1_SHIFT)

#define TCR_IRGN_NC		(TCR_IRGN0_NC | TCR_IRGN1_NC)
#define TCR_IRGN_WBWA		(TCR_IRGN0_WBWA | TCR_IRGN1_WBWA)
#define TCR_IRGN_WT		(TCR_IRGN0_WT | TCR_IRGN1_WT)
#define TCR_IRGN_WBnWA		(TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA)
#define TCR_IRGN_MASK		(TCR_IRGN0_MASK | TCR_IRGN1_MASK)

#define TCR_ORGN0_SHIFT		10
#define TCR_ORGN0_MASK		(UL(3) << TCR_ORGN0_SHIFT)
#define TCR_ORGN0_NC		(UL(0) << TCR_ORGN0_SHIFT)
#define TCR_ORGN0_WBWA		(UL(1) << TCR_ORGN0_SHIFT)
#define TCR_ORGN0_WT		(UL(2) << TCR_ORGN0_SHIFT)
#define TCR_ORGN0_WBnWA		(UL(3) << TCR_ORGN0_SHIFT)

#define TCR_ORGN1_SHIFT		26
#define TCR_ORGN1_MASK		(UL(3) << TCR_ORGN1_SHIFT)
#define TCR_ORGN1_NC		(UL(0) << TCR_ORGN1_SHIFT)
#define TCR_ORGN1_WBWA		(UL(1) << TCR_ORGN1_SHIFT)
#define TCR_ORGN1_WT		(UL(2) << TCR_ORGN1_SHIFT)
#define TCR_ORGN1_WBnWA		(UL(3) << TCR_ORGN1_SHIFT)

#define TCR_ORGN_NC		(TCR_ORGN0_NC | TCR_ORGN1_NC)
#define TCR_ORGN_WBWA		(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)
#define TCR_ORGN_WT		(TCR_ORGN0_WT | TCR_ORGN1_WT)
#define TCR_ORGN_WBnWA		(TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA)
#define TCR_ORGN_MASK		(TCR_ORGN0_MASK | TCR_ORGN1_MASK)

#define TCR_SH0_SHIFT		12
#define TCR_SH0_MASK		(UL(3) << TCR_SH0_SHIFT)
#define TCR_SH0_INNER		(UL(3) << TCR_SH0_SHIFT)

#define TCR_SH1_SHIFT		28
#define TCR_SH1_MASK		(UL(3) << TCR_SH1_SHIFT)
#define TCR_SH1_INNER		(UL(3) << TCR_SH1_SHIFT)
#define TCR_SHARED		(TCR_SH0_INNER | TCR_SH1_INNER)

#define TCR_TG0_SHIFT		14
#define TCR_TG0_MASK		(UL(3) << TCR_TG0_SHIFT)
#define TCR_TG0_4K		(UL(0) << TCR_TG0_SHIFT)
#define TCR_TG0_64K		(UL(1) << TCR_TG0_SHIFT)
#define TCR_TG0_16K		(UL(2) << TCR_TG0_SHIFT)

#define TCR_TG1_SHIFT		30
#define TCR_TG1_MASK		(UL(3) << TCR_TG1_SHIFT)
#define TCR_TG1_16K		(UL(1) << TCR_TG1_SHIFT)
#define TCR_TG1_4K		(UL(2) << TCR_TG1_SHIFT)
#define TCR_TG1_64K		(UL(3) << TCR_TG1_SHIFT)

#define TCR_A1			(UL(1) << 22)
#define TCR_ASID16		(UL(1) << 36)
#define TCR_TBI0		(UL(1) << 37)
#define TCR_HA			(UL(1) << 39)
#define TCR_HD			(UL(1) << 40)

#endif