OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:12 AM	rwxr-xr-x
📄 Kbuild	703 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 acenv.h	541 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 acpi.h	4.34 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 alternative.h	7.63 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 arch_gicv3.h	3.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 arch_timer.h	4.87 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 arm-cci.h	794 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-bug.h	1.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-uaccess.h	2.09 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 assembler.h	13.51 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 atomic.h	8.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic_ll_sc.h	10.61 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 atomic_lse.h	14.82 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 barrier.h	3.78 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 bitops.h	1.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitrev.h	452 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 boot.h	384 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 brk-imm.h	706 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	2.23 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cacheflush.h	4.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	1.35 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 clocksource.h	192 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	7.98 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compat.h	7.15 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compiler.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu.h	1.84 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpu_ops.h	2.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpucaps.h	1.87 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpufeature.h	19.14 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpuidle.h	401 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cputype.h	8.1 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 current.h	517 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 daifflags.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcc.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 debug-monitors.h	3.76 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 device.h	886 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	2.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dmi.h	850 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 efi.h	4.57 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 elf.h	5.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 esr.h	9.02 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 exception.h	1.21 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 exec.h	868 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable.h	815 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	1000 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.91 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 fpsimd.h	4.21 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 fpsimdmacros.h	5.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	1.92 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 futex.h	3.41 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hardirq.h	2.08 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hugetlb.h	2.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_breakpoint.h	4.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hwcap.h	1.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hypervisor.h	144 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 insn.h	16.03 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 io.h	7.72 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 irq.h	307 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_work.h	228 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	1.68 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kasan.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kernel-pgtable.h	4.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	2.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	3.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	1.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_arm.h	8.38 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_asm.h	4.26 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_coproc.h	2.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_emulate.h	10.38 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_host.h	15.73 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_hyp.h	5.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_mmio.h	1.3 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_mmu.h	11.72 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 linkage.h	114 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 lse.h	1.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 memblock.h	720 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 memory.h	9.16 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmu.h	2.76 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmu_context.h	6.35 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmzone.h	266 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	2.8 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 neon.h	815 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 numa.h	1.33 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 page-def.h	1.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	1.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 paravirt.h	458 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	878 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu.h	7.48 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 perf_event.h	3.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	3.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-hwdef.h	9.4 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtable-prot.h	4.38 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtable-types.h	1.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	21.55 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 probes.h	1022 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 proc-fns.h	1.21 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 processor.h	6.52 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ptdump.h	1.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	9 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 sdei.h	1.46 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 seccomp.h	714 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	1.46 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 shmparam.h	965 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal32.h	1.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 simd.h	1.39 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 smp.h	4.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp_plat.h	1.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sparsemem.h	771 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	3.33 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 spinlock_types.h	1.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stack_pointer.h	247 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackprotector.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	2.53 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 stage2_pgtable-nopmd.h	1.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stage2_pgtable-nopud.h	1.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stage2_pgtable.h	4.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stat.h	1.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	2.33 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 suspend.h	1.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sync_bitops.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	2.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sysreg.h	25.1 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 system_misc.h	1.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	3.93 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 timex.h	883 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	2.22 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tlbflush.h	5.38 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 topology.h	1.29 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 traps.h	3.33 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 uaccess.h	12.01 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 unistd.h	1.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd32.h	27.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uprobes.h	777 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso_datapage.h	1.53 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 vectors.h	1.75 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 virt.h	3 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 vmap_stack.h	769 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 word-at-a-time.h	2.22 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 xen	-	05/09/2024 07:14:16 AM	rwxr-xr-x

Editing: io.h

/*
 * Based on arch/arm/include/asm/io.h
 *
 * Copyright (C) 1996-2000 Russell King
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_IO_H
#define __ASM_IO_H

#ifdef __KERNEL__

#include <linux/types.h>

#include <asm/byteorder.h>
#include <asm/barrier.h>
#include <asm/memory.h>
#include <asm/pgtable.h>
#include <asm/early_ioremap.h>
#include <asm/alternative.h>
#include <asm/cpufeature.h>

#include <xen/xen.h>

/*
 * Generic IO read/write.  These perform native-endian accesses.
 */
#define __raw_writeb __raw_writeb
static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
{
	asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr));
}

#define __raw_writew __raw_writew
static inline void __raw_writew(u16 val, volatile void __iomem *addr)
{
	asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr));
}

#define __raw_writel __raw_writel
static inline void __raw_writel(u32 val, volatile void __iomem *addr)
{
	asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr));
}

#define __raw_writeq __raw_writeq
static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
{
	asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr));
}

#define __raw_readb __raw_readb
static inline u8 __raw_readb(const volatile void __iomem *addr)
{
	u8 val;
	asm volatile(ALTERNATIVE("ldrb %w0, [%1]",
				 "ldarb %w0, [%1]",
				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
		     : "=r" (val) : "r" (addr));
	return val;
}

#define __raw_readw __raw_readw
static inline u16 __raw_readw(const volatile void __iomem *addr)
{
	u16 val;

asm volatile(ALTERNATIVE("ldrh %w0, [%1]",
				 "ldarh %w0, [%1]",
				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
		     : "=r" (val) : "r" (addr));
	return val;
}

#define __raw_readl __raw_readl
static inline u32 __raw_readl(const volatile void __iomem *addr)
{
	u32 val;
	asm volatile(ALTERNATIVE("ldr %w0, [%1]",
				 "ldar %w0, [%1]",
				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
		     : "=r" (val) : "r" (addr));
	return val;
}

#define __raw_readq __raw_readq
static inline u64 __raw_readq(const volatile void __iomem *addr)
{
	u64 val;
	asm volatile(ALTERNATIVE("ldr %0, [%1]",
				 "ldar %0, [%1]",
				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
		     : "=r" (val) : "r" (addr));
	return val;
}

/* IO barriers */
#define __iormb(v)							\
({									\
	unsigned long tmp;						\
									\
	rmb();								\
									\
	/*								\
	 * Create a dummy control dependency from the IO read to any	\
	 * later instructions. This ensures that a subsequent call to	\
	 * udelay() will be ordered due to the ISB in get_cycles().	\
	 */								\
	asm volatile("eor	%0, %1, %1\n"				\
		     "cbnz	%0, ."					\
		     : "=r" (tmp) : "r" ((unsigned long)(v))		\
		     : "memory");					\
})

#define __iowmb()		wmb()

#define mmiowb()		do { } while (0)

/*
 * Relaxed I/O memory access primitives. These follow the Device memory
 * ordering rules but do not guarantee any ordering relative to Normal memory
 * accesses.
 */
#define readb_relaxed(c)	({ u8  __r = __raw_readb(c); __r; })
#define readw_relaxed(c)	({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
#define readl_relaxed(c)	({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
#define readq_relaxed(c)	({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })

#define writeb_relaxed(v,c)	((void)__raw_writeb((v),(c)))
#define writew_relaxed(v,c)	((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
#define writel_relaxed(v,c)	((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
#define writeq_relaxed(v,c)	((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))

/*
 * I/O memory access primitives. Reads are ordered relative to any
 * following Normal memory access. Writes are ordered relative to any prior
 * Normal memory access.
 */
#define readb(c)		({ u8  __v = readb_relaxed(c); __iormb(__v); __v; })
#define readw(c)		({ u16 __v = readw_relaxed(c); __iormb(__v); __v; })
#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(__v); __v; })
#define readq(c)		({ u64 __v = readq_relaxed(c); __iormb(__v); __v; })

#define writeb(v,c)		({ __iowmb(); writeb_relaxed((v),(c)); })
#define writew(v,c)		({ __iowmb(); writew_relaxed((v),(c)); })
#define writel(v,c)		({ __iowmb(); writel_relaxed((v),(c)); })
#define writeq(v,c)		({ __iowmb(); writeq_relaxed((v),(c)); })

/*
 *  I/O port access primitives.
 */
#define arch_has_dev_port()	(1)
#define IO_SPACE_LIMIT		(PCI_IO_SIZE - 1)
#define PCI_IOBASE		((void __iomem *)PCI_IO_START)

/*
 * String version of I/O memory access operations.
 */
extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t);
extern void __memcpy_toio(volatile void __iomem *, const void *, size_t);
extern void __memset_io(volatile void __iomem *, int, size_t);

#define memset_io(c,v,l)	__memset_io((c),(v),(l))
#define memcpy_fromio(a,c,l)	__memcpy_fromio((a),(c),(l))
#define memcpy_toio(c,a,l)	__memcpy_toio((c),(a),(l))

/*
 * I/O memory mapping functions.
 */
extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot);
extern void __iounmap(volatile void __iomem *addr);
extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);

#define ioremap(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
#define ioremap_nocache(addr, size)	__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
#define ioremap_wc(addr, size)		__ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
#define ioremap_wt(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
#define iounmap				__iounmap

/*
 * PCI configuration space mapping function.
 *
 * The PCI specification disallows posted write configuration transactions.
 * Add an arch specific pci_remap_cfgspace() definition that is implemented
 * through nGnRnE device memory attribute as recommended by the ARM v8
 * Architecture reference manual Issue A.k B2.8.2 "Device memory".
 */
#define pci_remap_cfgspace(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRnE))

/*
 * io{read,write}{16,32,64}be() macros
 */
#define ioread16be(p)		({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(__v); __v; })
#define ioread32be(p)		({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(__v); __v; })
#define ioread64be(p)		({ __u64 __v = be64_to_cpu((__force __be64)__raw_readq(p)); __iormb(__v); __v; })

#define iowrite16be(v,p)	({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
#define iowrite32be(v,p)	({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
#define iowrite64be(v,p)	({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })

#include <asm-generic/io.h>

/*
 * More restrictive address range checking than the default implementation
 * (PHYS_OFFSET and PHYS_MASK taken into account).
 */
#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);

extern int devmem_is_allowed(unsigned long pfn);

struct bio_vec;
extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
				      const struct bio_vec *vec2);
#define BIOVEC_PHYS_MERGEABLE(vec1, vec2)				\
	(__BIOVEC_PHYS_MERGEABLE(vec1, vec2) &&				\
	 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))

#endif	/* __KERNEL__ */
#endif	/* __ASM_IO_H */