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11/17/2022 06:42:15 AM
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Kbuild
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acenv.h
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acpi-ext.h
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agp.h
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asm-offsets.h
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asm-prototypes.h
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asmmacro.h
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atomic.h
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barrier.h
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clocksource.h
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cpu.h
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current.h
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cyclone.h
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delay.h
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device.h
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div64.h
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dma-mapping.h
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dma.h
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dmi.h
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early_ioremap.h
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elf.h
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emergency-restart.h
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esi.h
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exception.h
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export.h
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extable.h
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fb.h
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hardirq.h
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hpsim.h
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hugetlb.h
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hw_irq.h
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idle.h
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intrinsics.h
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io.h
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iommu.h
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iommu_table.h
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iosapic.h
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irq.h
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irq_regs.h
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irq_remapping.h
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irqflags.h
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kdebug.h
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kexec.h
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kmap_types.h
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kprobes.h
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kregs.h
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libata-portmap.h
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linkage.h
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local.h
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local64.h
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machvec.h
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machvec_dig.h
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machvec_dig_vtd.h
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machvec_hpsim.h
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machvec_hpzx1.h
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machvec_hpzx1_swiotlb.h
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machvec_init.h
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machvec_sn2.h
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machvec_uv.h
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mca.h
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mca_asm.h
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meminit.h
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mman.h
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mmu.h
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mmu_context.h
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mmzone.h
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module.h
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msidef.h
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native
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nodedata.h
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numa.h
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page.h
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pal.h
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param.h
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parport.h
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patch.h
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pci.h
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percpu.h
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perfmon.h
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pgalloc.h
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pgtable.h
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processor.h
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ptrace.h
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rwsem.h
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sal.h
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sections.h
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segment.h
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serial.h
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shmparam.h
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signal.h
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smp.h
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sn
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sparsemem.h
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spinlock.h
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spinlock_types.h
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string.h
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swiotlb.h
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switch_to.h
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syscall.h
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termios.h
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thread_info.h
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timex.h
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tlb.h
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tlbflush.h
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topology.h
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types.h
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uaccess.h
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unaligned.h
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uncached.h
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unistd.h
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unwind.h
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user.h
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ustack.h
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uv
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vga.h
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xor.h
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Editing: switch_to.h
Close
/* SPDX-License-Identifier: GPL-2.0 */ /* * Low-level task switching. This is based on information published in * the Processor Abstraction Layer and the System Abstraction Layer * manual. * * Copyright (C) 1998-2003 Hewlett-Packard Co * David Mosberger-Tang <davidm@hpl.hp.com> * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> */ #ifndef _ASM_IA64_SWITCH_TO_H #define _ASM_IA64_SWITCH_TO_H #include <linux/percpu.h> struct task_struct; /* * Context switch from one thread to another. If the two threads have * different address spaces, schedule() has already taken care of * switching to the new address space by calling switch_mm(). * * Disabling access to the fph partition and the debug-register * context switch MUST be done before calling ia64_switch_to() since a * newly created thread returns directly to * ia64_ret_from_syscall_clear_r8. */ extern struct task_struct *ia64_switch_to (void *next_task); extern void ia64_save_extra (struct task_struct *task); extern void ia64_load_extra (struct task_struct *task); #ifdef CONFIG_PERFMON DECLARE_PER_CPU(unsigned long, pfm_syst_info); # define PERFMON_IS_SYSWIDE() (__this_cpu_read(pfm_syst_info) & 0x1) #else # define PERFMON_IS_SYSWIDE() (0) #endif #define IA64_HAS_EXTRA_STATE(t) \ ((t)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID) \ || PERFMON_IS_SYSWIDE()) #define __switch_to(prev,next,last) do { \ if (IA64_HAS_EXTRA_STATE(prev)) \ ia64_save_extra(prev); \ if (IA64_HAS_EXTRA_STATE(next)) \ ia64_load_extra(next); \ ia64_psr(task_pt_regs(next))->dfh = !ia64_is_local_fpu_owner(next); \ (last) = ia64_switch_to((next)); \ } while (0) #ifdef CONFIG_SMP /* * In the SMP case, we save the fph state when context-switching away from a thread that * modified fph. This way, when the thread gets scheduled on another CPU, the CPU can * pick up the state from task->thread.fph, avoiding the complication of having to fetch * the latest fph state from another CPU. In other words: eager save, lazy restore. */ # define switch_to(prev,next,last) do { \ if (ia64_psr(task_pt_regs(prev))->mfh && ia64_is_local_fpu_owner(prev)) { \ ia64_psr(task_pt_regs(prev))->mfh = 0; \ (prev)->thread.flags |= IA64_THREAD_FPH_VALID; \ __ia64_save_fpu((prev)->thread.fph); \ } \ __switch_to(prev, next, last); \ /* "next" in old context is "current" in new context */ \ if (unlikely((current->thread.flags & IA64_THREAD_MIGRATION) && \ (task_cpu(current) != \ task_thread_info(current)->last_cpu))) { \ platform_migrate(current); \ task_thread_info(current)->last_cpu = task_cpu(current); \ } \ } while (0) #else # define switch_to(prev,next,last) __switch_to(prev, next, last) #endif #endif /* _ASM_IA64_SWITCH_TO_H */