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11/17/2022 06:42:15 AM
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Kbuild
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acenv.h
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acpi-ext.h
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acpi.h
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agp.h
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asm-offsets.h
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asm-prototypes.h
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asmmacro.h
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atomic.h
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barrier.h
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bitops.h
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bug.h
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bugs.h
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cacheflush.h
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checksum.h
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clocksource.h
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cpu.h
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cputime.h
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current.h
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cyclone.h
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delay.h
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device.h
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div64.h
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dma-mapping.h
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dma.h
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dmi.h
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early_ioremap.h
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elf.h
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emergency-restart.h
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esi.h
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exception.h
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export.h
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extable.h
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fb.h
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fpswa.h
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ftrace.h
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futex.h
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gcc_intrin.h
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hardirq.h
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hpsim.h
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hugetlb.h
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hw_irq.h
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idle.h
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intrinsics.h
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io.h
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iommu.h
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iommu_table.h
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iosapic.h
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irq.h
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irq_regs.h
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irq_remapping.h
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irqflags.h
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kdebug.h
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kexec.h
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kmap_types.h
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kprobes.h
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kregs.h
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libata-portmap.h
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linkage.h
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local.h
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local64.h
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machvec.h
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machvec_dig.h
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machvec_dig_vtd.h
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machvec_hpsim.h
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machvec_hpzx1.h
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machvec_hpzx1_swiotlb.h
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machvec_init.h
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machvec_sn2.h
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machvec_uv.h
684 bytes
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mca.h
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mca_asm.h
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meminit.h
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mman.h
432 bytes
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mmu.h
374 bytes
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mmu_context.h
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mmzone.h
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module.h
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msidef.h
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native
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nodedata.h
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numa.h
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page.h
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pal.h
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param.h
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parport.h
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patch.h
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pci.h
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percpu.h
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perfmon.h
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pgalloc.h
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pgtable.h
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processor.h
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ptrace.h
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rwsem.h
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sal.h
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sections.h
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segment.h
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serial.h
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shmparam.h
445 bytes
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signal.h
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smp.h
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sn
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11/17/2022 06:42:20 AM
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sparsemem.h
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spinlock.h
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spinlock_types.h
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string.h
659 bytes
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swiotlb.h
344 bytes
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switch_to.h
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syscall.h
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termios.h
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thread_info.h
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timex.h
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tlb.h
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tlbflush.h
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topology.h
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types.h
828 bytes
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uaccess.h
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unaligned.h
337 bytes
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uncached.h
463 bytes
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unistd.h
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unwind.h
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user.h
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ustack.h
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uv
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vga.h
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xor.h
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Editing: barrier.h
Close
/* SPDX-License-Identifier: GPL-2.0 */ /* * Memory barrier definitions. This is based on information published * in the Processor Abstraction Layer and the System Abstraction Layer * manual. * * Copyright (C) 1998-2003 Hewlett-Packard Co * David Mosberger-Tang <davidm@hpl.hp.com> * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> */ #ifndef _ASM_IA64_BARRIER_H #define _ASM_IA64_BARRIER_H #include <linux/compiler.h> /* * Macros to force memory ordering. In these descriptions, "previous" * and "subsequent" refer to program order; "visible" means that all * architecturally visible effects of a memory access have occurred * (at a minimum, this means the memory has been read or written). * * wmb(): Guarantees that all preceding stores to memory- * like regions are visible before any subsequent * stores and that all following stores will be * visible only after all previous stores. * rmb(): Like wmb(), but for reads. * mb(): wmb()/rmb() combo, i.e., all previous memory * accesses are visible before all subsequent * accesses and vice versa. This is also known as * a "fence." * * Note: "mb()" and its variants cannot be used as a fence to order * accesses to memory mapped I/O registers. For that, mf.a needs to * be used. However, we don't want to always use mf.a because (a) * it's (presumably) much slower than mf and (b) mf.a is supported for * sequential memory pages only. */ #define mb() ia64_mf() #define rmb() mb() #define wmb() mb() #define dma_rmb() mb() #define dma_wmb() mb() # define __smp_mb() mb() #define __smp_mb__before_atomic() barrier() #define __smp_mb__after_atomic() barrier() /* * IA64 GCC turns volatile stores into st.rel and volatile loads into ld.acq no * need for asm trickery! */ #define __smp_store_release(p, v) \ do { \ compiletime_assert_atomic_type(*p); \ barrier(); \ WRITE_ONCE(*p, v); \ } while (0) #define __smp_load_acquire(p) \ ({ \ typeof(*p) ___p1 = READ_ONCE(*p); \ compiletime_assert_atomic_type(*p); \ barrier(); \ ___p1; \ }) /* * The group barrier in front of the rsm & ssm are necessary to ensure * that none of the previous instructions in the same group are * affected by the rsm/ssm. */ #include <asm-generic/barrier.h> #endif /* _ASM_IA64_BARRIER_H */