OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:13 AM	rwxr-xr-x
📄 Kbuild	491 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 agp.h	434 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 apb.h	1.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	727 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	219 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic_32.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic_64.h	3.34 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 auxio.h	310 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 auxio_32.h	2.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 auxio_64.h	3.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 backoff.h	2.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	223 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier_32.h	160 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier_64.h	1.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bbc.h	9.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitext.h	631 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	219 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops_32.h	2.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops_64.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 btext.h	145 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	588 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 bugs.h	404 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	649 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	373 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush_32.h	1.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush_64.h	2.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cachetlb_32.h	882 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 chafsr.h	9.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	227 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum_32.h	6.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum_64.h	4.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 chmctrl.h	7.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clock.h	231 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 clocksource.h	407 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	223 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg_32.h	2.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg_64.h	5.13 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compat.h	6.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat_signal.h	565 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 contregs.h	1.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu_type.h	579 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpudata.h	378 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpudata_32.h	729 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpudata_64.h	1.13 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 current.h	991 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr.h	728 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcu.h	1.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	215 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay_32.h	907 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay_64.h	403 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 device.h	565 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	632 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	6.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ebus_dma.h	1.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ecc.h	4.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 eeprom.h	254 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	207 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf_32.h	3.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf_64.h	6.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 estate.h	2.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable_64.h	727 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	680 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fbio.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fhc.h	4.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	219 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy_32.h	9.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy_64.h	18.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpumacro.h	710 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	800 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	215 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex_32.h	82 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex_64.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	223 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq_32.h	334 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq_64.h	417 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 head.h	211 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 head_32.h	2.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 head_64.h	2.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hibernate.h	421 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	2.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hvtramp.h	782 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	88 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hypervisor.h	110.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	2.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 idprom.h	656 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 intr_queue.h	794 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io-unit.h	2.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	620 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io_32.h	3.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io_64.h	10.66 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ioctls.h	358 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 iommu.h	215 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 iommu_32.h	5.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 iommu_64.h	2.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	207 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_32.h	526 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_64.h	3.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	227 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags_32.h	1.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags_64.h	1.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug.h	219 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug_32.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug_64.h	393 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	1014 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	233 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	1.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ldc.h	4.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 leon.h	7.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 leon_amba.h	8.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 leon_pci.h	512 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 lsu.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 machines.h	1.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mbus.h	2.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc.h	298 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc_32.h	699 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc_64.h	689 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mdesc.h	2.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 memctrl.h	311 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mman.h	304 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	207 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_32.h	209 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_64.h	3.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	239 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context_32.h	1.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context_64.h	4.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone.h	393 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 msi.h	774 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mxcc.h	4.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nmi.h	354 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ns87303.h	3.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 obio.h	6.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 openprom.h	7.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 oplib.h	215 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 oplib_32.h	5.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 oplib_64.h	8.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	274 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_32.h	3.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_64.h	4.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 parport.h	5.68 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pbm.h	1.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	207 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci_32.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci_64.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pcic.h	5.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pcr.h	1.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu.h	219 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu_32.h	168 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu_64.h	515 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	802 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	223 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc_32.h	1.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc_64.h	2.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	223 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable_32.h	11.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable_64.h	30.71 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtsrmmu.h	6.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pil.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	231 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor_32.h	3.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor_64.h	7.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 prom.h	2.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 psr.h	1.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	4.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 qrwlock.h	205 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 qspinlock.h	215 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ross.h	5.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sbi.h	3.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 scratchpad.h	547 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 seccomp.h	225 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	289 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	1.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sfafsr.h	3.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sfp-machine.h	239 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sfp-machine_32.h	6.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sfp-machine_64.h	3.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	227 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam_32.h	253 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam_64.h	306 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sigcontext.h	2.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	835 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	207 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp_32.h	3.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp_64.h	1.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sparsemem.h	349 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	227 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_32.h	4.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_64.h	409 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	549 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spitfire.h	9.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	166 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 starfire.h	418 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string_32.h	405 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string_64.h	505 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sunbpp.h	3.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 swift.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	231 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to_32.h	3.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to_64.h	2.58 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 syscall.h	3.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscalls.h	307 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 termbits.h	198 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 termios.h	4.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	239 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info_32.h	3.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info_64.h	7.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timer.h	215 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 timer_32.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timer_64.h	2.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	215 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex_32.h	266 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 timex_64.h	423 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	207 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb_32.h	520 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb_64.h	913 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	227 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush_32.h	621 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush_64.h	1.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	227 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology_32.h	170 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology_64.h	1.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 trap_block.h	6.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	577 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tsb.h	12.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tsunami.h	1.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ttable.h	20.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 turbosparc.h	3.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	363 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess_32.h	8.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess_64.h	6.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	339 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 upa.h	3.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uprobes.h	1.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	102 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vaddrs.h	2.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	662 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	964 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 viking.h	8.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vio.h	11.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 visasm.h	1.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
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Editing: spitfire.h

/* SPDX-License-Identifier: GPL-2.0 */
/* spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
 *
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 */

#ifndef _SPARC64_SPITFIRE_H
#define _SPARC64_SPITFIRE_H

#ifdef CONFIG_SPARC64

#include <asm/asi.h>

/* The following register addresses are accessible via ASI_DMMU
 * and ASI_IMMU, that is there is a distinct and unique copy of
 * each these registers for each TLB.
 */
#define TSB_TAG_TARGET		0x0000000000000000 /* All chips				*/
#define TLB_SFSR		0x0000000000000018 /* All chips				*/
#define TSB_REG			0x0000000000000028 /* All chips				*/
#define TLB_TAG_ACCESS		0x0000000000000030 /* All chips				*/
#define VIRT_WATCHPOINT		0x0000000000000038 /* All chips				*/
#define PHYS_WATCHPOINT		0x0000000000000040 /* All chips				*/
#define TSB_EXTENSION_P		0x0000000000000048 /* Ultra-III and later		*/
#define TSB_EXTENSION_S		0x0000000000000050 /* Ultra-III and later, D-TLB only	*/
#define TSB_EXTENSION_N		0x0000000000000058 /* Ultra-III and later		*/
#define TLB_TAG_ACCESS_EXT	0x0000000000000060 /* Ultra-III+ and later		*/

/* These registers only exist as one entity, and are accessed
 * via ASI_DMMU only.
 */
#define PRIMARY_CONTEXT		0x0000000000000008
#define SECONDARY_CONTEXT	0x0000000000000010
#define DMMU_SFAR		0x0000000000000020
#define VIRT_WATCHPOINT		0x0000000000000038
#define PHYS_WATCHPOINT		0x0000000000000040

#define SPITFIRE_HIGHEST_LOCKED_TLBENT	(64 - 1)
#define CHEETAH_HIGHEST_LOCKED_TLBENT	(16 - 1)

#define L1DCACHE_SIZE		0x4000

#define SUN4V_CHIP_INVALID	0x00
#define SUN4V_CHIP_NIAGARA1	0x01
#define SUN4V_CHIP_NIAGARA2	0x02
#define SUN4V_CHIP_NIAGARA3	0x03
#define SUN4V_CHIP_NIAGARA4	0x04
#define SUN4V_CHIP_NIAGARA5	0x05
#define SUN4V_CHIP_SPARC_M6	0x06
#define SUN4V_CHIP_SPARC_M7	0x07
#define SUN4V_CHIP_SPARC_M8	0x08
#define SUN4V_CHIP_SPARC64X	0x8a
#define SUN4V_CHIP_SPARC_SN	0x8b
#define SUN4V_CHIP_UNKNOWN	0xff

/*
 * The following CPU_ID_xxx constants are used
 * to identify the CPU type in the setup phase
 * (see head_64.S)
 */
#define CPU_ID_NIAGARA1		('1')
#define CPU_ID_NIAGARA2		('2')
#define CPU_ID_NIAGARA3		('3')
#define CPU_ID_NIAGARA4		('4')
#define CPU_ID_NIAGARA5		('5')
#define CPU_ID_M6		('6')
#define CPU_ID_M7		('7')
#define CPU_ID_M8		('8')
#define CPU_ID_SONOMA1		('N')

#ifndef __ASSEMBLY__

enum ultra_tlb_layout {
	spitfire = 0,
	cheetah = 1,
	cheetah_plus = 2,
	hypervisor = 3,
};

extern enum ultra_tlb_layout tlb_type;

extern int sun4v_chip_type;

extern int cheetah_pcache_forced_on;
void cheetah_enable_pcache(void);

#define sparc64_highest_locked_tlbent()	\
	(tlb_type == spitfire ? \
	 SPITFIRE_HIGHEST_LOCKED_TLBENT : \
	 CHEETAH_HIGHEST_LOCKED_TLBENT)

extern int num_kernel_image_mappings;

/* The data cache is write through, so this just invalidates the
 * specified line.
 */
static inline void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
{
	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG));
}

/* The instruction cache lines are flushed with this, but note that
 * this does not flush the pipeline.  It is possible for a line to
 * get flushed but stale instructions to still be in the pipeline,
 * a flush instruction (to any address) is sufficient to handle
 * this issue after the line is invalidated.
 */
static inline void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
{
	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
}

static inline unsigned long spitfire_get_dtlb_data(int entry)
{
	unsigned long data;

__asm__ __volatile__("ldxa	[%1] %2, %0"
			     : "=r" (data)
			     : "r" (entry << 3), "i" (ASI_DTLB_DATA_ACCESS));

/* Clear TTE diag bits. */
	data &= ~0x0003fe0000000000UL;

return data;
}

static inline unsigned long spitfire_get_dtlb_tag(int entry)
{
	unsigned long tag;

__asm__ __volatile__("ldxa	[%1] %2, %0"
			     : "=r" (tag)
			     : "r" (entry << 3), "i" (ASI_DTLB_TAG_READ));
	return tag;
}

static inline void spitfire_put_dtlb_data(int entry, unsigned long data)
{
	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (data), "r" (entry << 3),
			       "i" (ASI_DTLB_DATA_ACCESS));
}

static inline unsigned long spitfire_get_itlb_data(int entry)
{
	unsigned long data;

__asm__ __volatile__("ldxa	[%1] %2, %0"
			     : "=r" (data)
			     : "r" (entry << 3), "i" (ASI_ITLB_DATA_ACCESS));

/* Clear TTE diag bits. */
	data &= ~0x0003fe0000000000UL;

return data;
}

static inline unsigned long spitfire_get_itlb_tag(int entry)
{
	unsigned long tag;

__asm__ __volatile__("ldxa	[%1] %2, %0"
			     : "=r" (tag)
			     : "r" (entry << 3), "i" (ASI_ITLB_TAG_READ));
	return tag;
}

static inline void spitfire_put_itlb_data(int entry, unsigned long data)
{
	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (data), "r" (entry << 3),
			       "i" (ASI_ITLB_DATA_ACCESS));
}

static inline void spitfire_flush_dtlb_nucleus_page(unsigned long page)
{
	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP));
}

static inline void spitfire_flush_itlb_nucleus_page(unsigned long page)
{
	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (page | 0x20), "i" (ASI_IMMU_DEMAP));
}

/* Cheetah has "all non-locked" tlb flushes. */
static inline void cheetah_flush_dtlb_all(void)
{
	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (0x80), "i" (ASI_DMMU_DEMAP));
}

static inline void cheetah_flush_itlb_all(void)
{
	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (0x80), "i" (ASI_IMMU_DEMAP));
}

/* Cheetah has a 4-tlb layout so direct access is a bit different.
 * The first two TLBs are fully assosciative, hold 16 entries, and are
 * used only for locked and >8K sized translations.  One exists for
 * data accesses and one for instruction accesses.
 *
 * The third TLB is for data accesses to 8K non-locked translations, is
 * 2 way assosciative, and holds 512 entries.  The fourth TLB is for
 * instruction accesses to 8K non-locked translations, is 2 way
 * assosciative, and holds 128 entries.
 *
 * Cheetah has some bug where bogus data can be returned from
 * ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
 * the problem for me. -DaveM
 */
static inline unsigned long cheetah_get_ldtlb_data(int entry)
{
	unsigned long data;

__asm__ __volatile__("ldxa	[%1] %2, %%g0\n\t"
			     "ldxa	[%1] %2, %0"
			     : "=r" (data)
			     : "r" ((0 << 16) | (entry << 3)),
			     "i" (ASI_DTLB_DATA_ACCESS));

return data;
}

static inline unsigned long cheetah_get_litlb_data(int entry)
{
	unsigned long data;

__asm__ __volatile__("ldxa	[%1] %2, %%g0\n\t"
			     "ldxa	[%1] %2, %0"
			     : "=r" (data)
			     : "r" ((0 << 16) | (entry << 3)),
			     "i" (ASI_ITLB_DATA_ACCESS));

return data;
}

static inline unsigned long cheetah_get_ldtlb_tag(int entry)
{
	unsigned long tag;

__asm__ __volatile__("ldxa	[%1] %2, %0"
			     : "=r" (tag)
			     : "r" ((0 << 16) | (entry << 3)),
			     "i" (ASI_DTLB_TAG_READ));

return tag;
}

static inline unsigned long cheetah_get_litlb_tag(int entry)
{
	unsigned long tag;

__asm__ __volatile__("ldxa	[%1] %2, %0"
			     : "=r" (tag)
			     : "r" ((0 << 16) | (entry << 3)),
			     "i" (ASI_ITLB_TAG_READ));

return tag;
}

static inline void cheetah_put_ldtlb_data(int entry, unsigned long data)
{
	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (data),
			       "r" ((0 << 16) | (entry << 3)),
			       "i" (ASI_DTLB_DATA_ACCESS));
}

static inline void cheetah_put_litlb_data(int entry, unsigned long data)
{
	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (data),
			       "r" ((0 << 16) | (entry << 3)),
			       "i" (ASI_ITLB_DATA_ACCESS));
}

static inline unsigned long cheetah_get_dtlb_data(int entry, int tlb)
{
	unsigned long data;

__asm__ __volatile__("ldxa	[%1] %2, %%g0\n\t"
			     "ldxa	[%1] %2, %0"
			     : "=r" (data)
			     : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_DATA_ACCESS));

return data;
}

static inline unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
{
	unsigned long tag;

__asm__ __volatile__("ldxa	[%1] %2, %0"
			     : "=r" (tag)
			     : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_TAG_READ));
	return tag;
}

static inline void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
{
	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (data),
			       "r" ((tlb << 16) | (entry << 3)),
			       "i" (ASI_DTLB_DATA_ACCESS));
}

static inline unsigned long cheetah_get_itlb_data(int entry)
{
	unsigned long data;

__asm__ __volatile__("ldxa	[%1] %2, %%g0\n\t"
			     "ldxa	[%1] %2, %0"
			     : "=r" (data)
			     : "r" ((2 << 16) | (entry << 3)),
                               "i" (ASI_ITLB_DATA_ACCESS));

return data;
}

static inline unsigned long cheetah_get_itlb_tag(int entry)
{
	unsigned long tag;

__asm__ __volatile__("ldxa	[%1] %2, %0"
			     : "=r" (tag)
			     : "r" ((2 << 16) | (entry << 3)), "i" (ASI_ITLB_TAG_READ));
	return tag;
}

static inline void cheetah_put_itlb_data(int entry, unsigned long data)
{
	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
			     "membar	#Sync"
			     : /* No outputs */
			     : "r" (data), "r" ((2 << 16) | (entry << 3)),
			       "i" (ASI_ITLB_DATA_ACCESS));
}

#endif /* !(__ASSEMBLY__) */
#endif /* CONFIG_SPARC64 */
#endif /* !(_SPARC64_SPITFIRE_H) */