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05/09/2024 07:14:13 AM
rwxr-xr-x
📄
Kbuild
491 bytes
06/16/2023 05:32:39 PM
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agp.h
434 bytes
01/28/2018 09:20:33 PM
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apb.h
1.06 KB
01/28/2018 09:20:33 PM
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asm-offsets.h
35 bytes
01/28/2018 09:20:33 PM
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asm-prototypes.h
727 bytes
01/28/2018 09:20:33 PM
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asm.h
1.08 KB
01/28/2018 09:20:33 PM
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asmmacro.h
1.16 KB
01/28/2018 09:20:33 PM
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atomic.h
219 bytes
01/28/2018 09:20:33 PM
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atomic_32.h
2.26 KB
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atomic_64.h
3.34 KB
06/16/2023 05:32:39 PM
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auxio.h
310 bytes
01/28/2018 09:20:33 PM
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auxio_32.h
2.55 KB
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auxio_64.h
3.18 KB
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backoff.h
2.7 KB
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barrier.h
223 bytes
01/28/2018 09:20:33 PM
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barrier_32.h
160 bytes
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barrier_64.h
1.96 KB
01/28/2018 09:20:33 PM
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bbc.h
9.76 KB
01/28/2018 09:20:33 PM
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bitext.h
631 bytes
01/28/2018 09:20:33 PM
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bitops.h
219 bytes
01/28/2018 09:20:33 PM
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bitops_32.h
2.79 KB
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bitops_64.h
1.64 KB
01/28/2018 09:20:33 PM
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btext.h
145 bytes
01/28/2018 09:20:33 PM
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bug.h
588 bytes
06/16/2023 05:32:39 PM
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bugs.h
404 bytes
01/28/2018 09:20:33 PM
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cache.h
649 bytes
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cacheflush.h
373 bytes
01/28/2018 09:20:33 PM
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cacheflush_32.h
1.97 KB
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cacheflush_64.h
2.56 KB
01/28/2018 09:20:33 PM
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cachetlb_32.h
882 bytes
01/28/2018 09:20:33 PM
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chafsr.h
9.48 KB
01/28/2018 09:20:33 PM
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checksum.h
227 bytes
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checksum_32.h
6.81 KB
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checksum_64.h
4.4 KB
01/28/2018 09:20:33 PM
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chmctrl.h
7.91 KB
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clock.h
231 bytes
01/28/2018 09:20:33 PM
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clocksource.h
407 bytes
01/28/2018 09:20:33 PM
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cmpxchg.h
223 bytes
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cmpxchg_32.h
2.4 KB
01/28/2018 09:20:33 PM
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cmpxchg_64.h
5.13 KB
06/16/2023 05:32:39 PM
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compat.h
6.45 KB
01/28/2018 09:20:33 PM
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compat_signal.h
565 bytes
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contregs.h
1.9 KB
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cpu_type.h
579 bytes
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cpudata.h
378 bytes
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cpudata_32.h
729 bytes
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cpudata_64.h
1.13 KB
06/16/2023 05:32:39 PM
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current.h
991 bytes
01/28/2018 09:20:33 PM
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dcr.h
728 bytes
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dcu.h
1.48 KB
01/28/2018 09:20:33 PM
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delay.h
215 bytes
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delay_32.h
907 bytes
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delay_64.h
403 bytes
01/28/2018 09:20:33 PM
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device.h
565 bytes
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dma-mapping.h
632 bytes
01/28/2018 09:20:33 PM
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dma.h
6.6 KB
01/28/2018 09:20:33 PM
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ebus_dma.h
1.07 KB
01/28/2018 09:20:33 PM
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ecc.h
4.34 KB
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eeprom.h
254 bytes
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elf.h
207 bytes
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elf_32.h
3.19 KB
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elf_64.h
6.47 KB
01/28/2018 09:20:33 PM
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estate.h
2.23 KB
01/28/2018 09:20:33 PM
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extable_64.h
727 bytes
01/28/2018 09:20:33 PM
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fb.h
680 bytes
01/28/2018 09:20:33 PM
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fbio.h
2.26 KB
01/28/2018 09:20:33 PM
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fhc.h
4.43 KB
01/28/2018 09:20:33 PM
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floppy.h
219 bytes
01/28/2018 09:20:33 PM
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floppy_32.h
9.74 KB
01/28/2018 09:20:33 PM
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floppy_64.h
18.83 KB
01/28/2018 09:20:33 PM
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fpumacro.h
710 bytes
01/28/2018 09:20:33 PM
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ftrace.h
800 bytes
01/28/2018 09:20:33 PM
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futex.h
215 bytes
01/28/2018 09:20:33 PM
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📄
futex_32.h
82 bytes
01/28/2018 09:20:33 PM
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futex_64.h
2.15 KB
01/28/2018 09:20:33 PM
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hardirq.h
223 bytes
01/28/2018 09:20:33 PM
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📄
hardirq_32.h
334 bytes
01/28/2018 09:20:33 PM
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hardirq_64.h
417 bytes
01/28/2018 09:20:33 PM
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head.h
211 bytes
01/28/2018 09:20:33 PM
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head_32.h
2.56 KB
01/28/2018 09:20:33 PM
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head_64.h
2.13 KB
01/28/2018 09:20:33 PM
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hibernate.h
421 bytes
01/28/2018 09:20:33 PM
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highmem.h
2.02 KB
01/28/2018 09:20:33 PM
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hugetlb.h
2.09 KB
01/28/2018 09:20:33 PM
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hvtramp.h
782 bytes
01/28/2018 09:20:33 PM
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hw_irq.h
88 bytes
01/28/2018 09:20:33 PM
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hypervisor.h
110.71 KB
01/28/2018 09:20:33 PM
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📄
ide.h
2.19 KB
01/28/2018 09:20:33 PM
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📄
idprom.h
656 bytes
01/28/2018 09:20:33 PM
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📄
intr_queue.h
794 bytes
01/28/2018 09:20:33 PM
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📄
io-unit.h
2.41 KB
01/28/2018 09:20:33 PM
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📄
io.h
620 bytes
01/28/2018 09:20:33 PM
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io_32.h
3.51 KB
01/28/2018 09:20:33 PM
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io_64.h
10.66 KB
06/16/2023 05:32:39 PM
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📄
ioctls.h
358 bytes
01/28/2018 09:20:33 PM
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iommu.h
215 bytes
01/28/2018 09:20:33 PM
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📄
iommu_32.h
5.73 KB
01/28/2018 09:20:33 PM
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iommu_64.h
2.43 KB
01/28/2018 09:20:33 PM
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📄
irq.h
207 bytes
01/28/2018 09:20:33 PM
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📄
irq_32.h
526 bytes
01/28/2018 09:20:33 PM
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irq_64.h
3.06 KB
01/28/2018 09:20:33 PM
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irqflags.h
227 bytes
01/28/2018 09:20:33 PM
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📄
irqflags_32.h
1.03 KB
01/28/2018 09:20:33 PM
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irqflags_64.h
1.91 KB
01/28/2018 09:20:33 PM
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jump_label.h
1.01 KB
01/28/2018 09:20:33 PM
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kdebug.h
219 bytes
01/28/2018 09:20:33 PM
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kdebug_32.h
1.99 KB
01/28/2018 09:20:33 PM
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kdebug_64.h
393 bytes
01/28/2018 09:20:33 PM
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📄
kgdb.h
1014 bytes
01/28/2018 09:20:33 PM
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📄
kmap_types.h
233 bytes
01/28/2018 09:20:33 PM
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kprobes.h
1.41 KB
01/28/2018 09:20:33 PM
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ldc.h
4.37 KB
01/28/2018 09:20:33 PM
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leon.h
7.37 KB
01/28/2018 09:20:33 PM
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📄
leon_amba.h
8.09 KB
01/28/2018 09:20:33 PM
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leon_pci.h
512 bytes
01/28/2018 09:20:33 PM
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lsu.h
1.04 KB
01/28/2018 09:20:33 PM
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📄
machines.h
1.5 KB
01/28/2018 09:20:33 PM
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mbus.h
2.93 KB
01/28/2018 09:20:33 PM
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mc146818rtc.h
298 bytes
01/28/2018 09:20:33 PM
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mc146818rtc_32.h
699 bytes
01/28/2018 09:20:33 PM
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mc146818rtc_64.h
689 bytes
01/28/2018 09:20:33 PM
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mdesc.h
2.99 KB
01/28/2018 09:20:33 PM
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memctrl.h
311 bytes
01/28/2018 09:20:33 PM
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mman.h
304 bytes
01/28/2018 09:20:33 PM
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mmu.h
207 bytes
01/28/2018 09:20:33 PM
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mmu_32.h
209 bytes
01/28/2018 09:20:33 PM
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mmu_64.h
3.14 KB
01/28/2018 09:20:33 PM
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📄
mmu_context.h
239 bytes
01/28/2018 09:20:33 PM
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mmu_context_32.h
1.07 KB
01/28/2018 09:20:33 PM
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mmu_context_64.h
4.15 KB
01/28/2018 09:20:33 PM
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mmzone.h
393 bytes
01/28/2018 09:20:33 PM
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msi.h
774 bytes
01/28/2018 09:20:33 PM
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mxcc.h
4.33 KB
01/28/2018 09:20:33 PM
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nmi.h
354 bytes
01/28/2018 09:20:33 PM
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ns87303.h
3.22 KB
01/28/2018 09:20:33 PM
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obio.h
6.26 KB
01/28/2018 09:20:33 PM
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openprom.h
7.3 KB
01/28/2018 09:20:33 PM
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oplib.h
215 bytes
01/28/2018 09:20:33 PM
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oplib_32.h
5.92 KB
01/28/2018 09:20:33 PM
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oplib_64.h
8.12 KB
01/28/2018 09:20:33 PM
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page.h
274 bytes
01/28/2018 09:20:33 PM
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page_32.h
3.91 KB
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page_64.h
4.49 KB
01/28/2018 09:20:33 PM
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parport.h
5.68 KB
06/16/2023 05:32:39 PM
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pbm.h
1.47 KB
01/28/2018 09:20:33 PM
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pci.h
207 bytes
01/28/2018 09:20:33 PM
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pci_32.h
1.09 KB
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pci_64.h
1.49 KB
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pcic.h
5.77 KB
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pcr.h
1.85 KB
01/28/2018 09:20:33 PM
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percpu.h
219 bytes
01/28/2018 09:20:33 PM
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percpu_32.h
168 bytes
01/28/2018 09:20:33 PM
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percpu_64.h
515 bytes
01/28/2018 09:20:33 PM
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perf_event.h
802 bytes
01/28/2018 09:20:33 PM
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pgalloc.h
223 bytes
01/28/2018 09:20:33 PM
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pgalloc_32.h
1.91 KB
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pgalloc_64.h
2.85 KB
01/28/2018 09:20:33 PM
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pgtable.h
223 bytes
01/28/2018 09:20:33 PM
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pgtable_32.h
11.35 KB
01/28/2018 09:20:33 PM
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pgtable_64.h
30.71 KB
06/16/2023 05:32:39 PM
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pgtsrmmu.h
6.05 KB
01/28/2018 09:20:33 PM
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pil.h
1.08 KB
01/28/2018 09:20:33 PM
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processor.h
231 bytes
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processor_32.h
3.13 KB
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processor_64.h
7.58 KB
01/28/2018 09:20:33 PM
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prom.h
2.02 KB
01/28/2018 09:20:33 PM
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psr.h
1.38 KB
01/28/2018 09:20:33 PM
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ptrace.h
4.19 KB
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qrwlock.h
205 bytes
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qspinlock.h
215 bytes
01/28/2018 09:20:33 PM
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ross.h
5.52 KB
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sbi.h
3.34 KB
01/28/2018 09:20:33 PM
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scratchpad.h
547 bytes
01/28/2018 09:20:33 PM
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seccomp.h
225 bytes
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sections.h
289 bytes
01/28/2018 09:20:33 PM
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setup.h
1.52 KB
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sfafsr.h
3.14 KB
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sfp-machine.h
239 bytes
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sfp-machine_32.h
6.79 KB
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sfp-machine_64.h
3.1 KB
01/28/2018 09:20:33 PM
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shmparam.h
227 bytes
01/28/2018 09:20:33 PM
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shmparam_32.h
253 bytes
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shmparam_64.h
306 bytes
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sigcontext.h
2.55 KB
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signal.h
835 bytes
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smp.h
207 bytes
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smp_32.h
3.29 KB
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smp_64.h
1.84 KB
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sparsemem.h
349 bytes
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spinlock.h
227 bytes
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spinlock_32.h
4.22 KB
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spinlock_64.h
409 bytes
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spinlock_types.h
549 bytes
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spitfire.h
9.73 KB
01/28/2018 09:20:33 PM
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stacktrace.h
166 bytes
01/28/2018 09:20:33 PM
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starfire.h
418 bytes
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string.h
1.13 KB
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string_32.h
405 bytes
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string_64.h
505 bytes
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sunbpp.h
3.27 KB
01/28/2018 09:20:33 PM
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swift.h
3.07 KB
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switch_to.h
231 bytes
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switch_to_32.h
3.53 KB
01/28/2018 09:20:33 PM
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switch_to_64.h
2.58 KB
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syscall.h
3.41 KB
01/28/2018 09:20:33 PM
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syscalls.h
307 bytes
01/28/2018 09:20:33 PM
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termbits.h
198 bytes
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termios.h
4.94 KB
01/28/2018 09:20:33 PM
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thread_info.h
239 bytes
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thread_info_32.h
3.66 KB
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thread_info_64.h
7.84 KB
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timer.h
215 bytes
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Editing: dma.h
Close
/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_SPARC_DMA_H #define _ASM_SPARC_DMA_H /* These are irrelevant for Sparc DMA, but we leave it in so that * things can compile. */ #define MAX_DMA_CHANNELS 8 #define DMA_MODE_READ 1 #define DMA_MODE_WRITE 2 #define MAX_DMA_ADDRESS (~0UL) /* Useful constants */ #define SIZE_16MB (16*1024*1024) #define SIZE_64K (64*1024) /* SBUS DMA controller reg offsets */ #define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */ #define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */ #define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */ #define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */ /* Fields in the cond_reg register */ /* First, the version identification bits */ #define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */ #define DMA_VERS0 0x00000000 /* Sunray DMA version */ #define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */ #define DMA_VERS1 0x80000000 /* DMA rev 1 */ #define DMA_VERS2 0xa0000000 /* DMA rev 2 */ #define DMA_VERHME 0xb0000000 /* DMA hme gate array */ #define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */ #define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */ #define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */ #define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */ #define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */ #define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */ #define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */ #define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */ #define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */ #define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */ #define DMA_ST_WRITE 0x00000100 /* write from device to memory */ #define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */ #define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */ #define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */ #define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */ #define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */ #define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */ #define DMA_TERM_CNTR 0x00004000 /* Terminal counter */ #define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */ #define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */ #define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */ #define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */ #define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */ #define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */ #define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */ #define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */ #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */ #define DMA_BRST64 0x000c0000 /* SCSI: 64byte bursts (HME on UltraSparc only) */ #define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */ #define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */ #define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */ #define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */ #define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */ #define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */ #define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */ #define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */ #define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */ #define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */ #define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */ #define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */ #define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */ #define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */ /* Values describing the burst-size property from the PROM */ #define DMA_BURST1 0x01 #define DMA_BURST2 0x02 #define DMA_BURST4 0x04 #define DMA_BURST8 0x08 #define DMA_BURST16 0x10 #define DMA_BURST32 0x20 #define DMA_BURST64 0x40 #define DMA_BURSTBITS 0x7f /* From PCI */ #ifdef CONFIG_PCI extern int isa_dma_bridge_buggy; #else #define isa_dma_bridge_buggy (0) #endif #ifdef CONFIG_SPARC32 /* Routines for data transfer buffers. */ struct device; struct scatterlist; struct sparc32_dma_ops { __u32 (*get_scsi_one)(struct device *, char *, unsigned long); void (*get_scsi_sgl)(struct device *, struct scatterlist *, int); void (*release_scsi_one)(struct device *, __u32, unsigned long); void (*release_scsi_sgl)(struct device *, struct scatterlist *,int); #ifdef CONFIG_SBUS int (*map_dma_area)(struct device *, dma_addr_t *, unsigned long, unsigned long, int); void (*unmap_dma_area)(struct device *, unsigned long, int); #endif }; extern const struct sparc32_dma_ops *sparc32_dma_ops; #define mmu_get_scsi_one(dev,vaddr,len) \ sparc32_dma_ops->get_scsi_one(dev, vaddr, len) #define mmu_get_scsi_sgl(dev,sg,sz) \ sparc32_dma_ops->get_scsi_sgl(dev, sg, sz) #define mmu_release_scsi_one(dev,vaddr,len) \ sparc32_dma_ops->release_scsi_one(dev, vaddr,len) #define mmu_release_scsi_sgl(dev,sg,sz) \ sparc32_dma_ops->release_scsi_sgl(dev, sg, sz) #ifdef CONFIG_SBUS /* * mmu_map/unmap are provided by iommu/iounit; Invalid to call on IIep. * * The mmu_map_dma_area establishes two mappings in one go. * These mappings point to pages normally mapped at 'va' (linear address). * First mapping is for CPU visible address at 'a', uncached. * This is an alias, but it works because it is an uncached mapping. * Second mapping is for device visible address, or "bus" address. * The bus address is returned at '*pba'. * * These functions seem distinct, but are hard to split. * On sun4m, page attributes depend on the CPU type, so we have to * know if we are mapping RAM or I/O, so it has to be an additional argument * to a separate mapping function for CPU visible mappings. */ #define sbus_map_dma_area(dev,pba,va,a,len) \ sparc32_dma_ops->map_dma_area(dev, pba, va, a, len) #define sbus_unmap_dma_area(dev,ba,len) \ sparc32_dma_ops->unmap_dma_area(dev, ba, len) #endif /* CONFIG_SBUS */ #endif #endif /* !(_ASM_SPARC_DMA_H) */