OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:13 AM	rwxr-xr-x
📄 Kbuild	577 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 abi.h	853 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 addrspace.h	4.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amon.h	409 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 arch_hweight.h	792 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-eva.h	6.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	197 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm.h	8.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro-32.h	2.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro-64.h	1.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro.h	14.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	19.73 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 barrier.h	8.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcache.h	2.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	15.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitrev.h	608 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bmips-spaces.h	268 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bmips.h	3.45 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 bootinfo.h	5.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 branch.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 break.h	787 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	759 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	944 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	546 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	4.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheops.h	3.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cdmm.h	3.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cevt-r4k.h	823 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	6.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clock.h	997 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 clocksource.h	884 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmp.h	492 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	5.28 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compat-signal.h	640 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat.h	6.66 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compiler.h	2.96 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cop2.h	1.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu-features.h	19.46 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpu-info.h	5.84 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpu-type.h	4.13 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpu.h	15.54 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpufeature.h	717 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 debug.h	654 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 dec	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 delay.h	841 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 device.h	347 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 div64.h	2.17 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 dma-coherence.h	813 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	981 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	9.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ds1287.h	1019 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dsemul.h	3.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dsp.h	1.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 edac.h	819 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	15.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 emma	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 errno.h	429 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 eva.h	796 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 exec.h	579 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable.h	241 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	372 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpregdef.h	2.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu.h	5.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu_emulator.h	5.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	2.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	4.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 fw	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 gio_device.h	1.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gt64120.h	19.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	544 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hazards.h	8.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	1.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hpet.h	1.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb.h	2.76 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hw_irq.h	475 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 i8259.h	2.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	330 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 idle.h	689 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 inst.h	2.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	18.44 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 ip32	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 irq.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_cpu.h	708 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_gt641xx.h	2.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_regs.h	744 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	4.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 isa-rev.h	556 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 isadep.h	603 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 jazz.h	8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jazzdma.h	2.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	1.4 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kdebug.h	303 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	1.53 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kgdb.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	221 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_host.h	37.88 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_para.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 lasat	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 linkage.h	306 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 llsc.h	623 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 local.h	4.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m48t37.h	732 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 maar.h	4.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 mach-ar7	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ath25	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ath79	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-au1x00	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-bcm47xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-bcm63xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-bmips	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-cavium-octeon	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-cobalt	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-db1x00	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-dec	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-emma2rh	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-generic	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ip22	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ip27	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ip28	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ip32	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-jazz	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-jz4740	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-lantiq	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-lasat	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-loongson32	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-loongson64	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-malta	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-netlogic	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-paravirt	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-pic32	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-pistachio	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-pmcs-msp71xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-pnx833x	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ralink	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-rc32434	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-rm	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-sibyte	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-tx39xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-tx49xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-vr41xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-xilfpga	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 machine.h	2.93 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mc146818-time.h	3.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc.h	450 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 mips-boards	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 mips-cm.h	15.86 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mips-cpc.h	5.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips-cps.h	6.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips-gic.h	12.3 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mips-r2-to-r6-emul.h	2.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips_machine.h	1.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips_mt.h	707 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mipsmtregs.h	10.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mipsprom.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mipsregs.h	88.1 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmu.h	550 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmu_context.h	5.41 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmzone.h	561 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 module.h	4.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msa.h	8.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msc01_ic.h	6.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 netlogic	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 nile4.h	10.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 octeon	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 paccess.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	7.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 pci	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 pci.h	4.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	482 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	3.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-32.h	7.31 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtable-64.h	10.87 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtable-bits.h	7.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	17.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm-cps.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm.h	3.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmon.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 prefetch.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	11.71 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 prom.h	845 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	5.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 r4k-timer.h	604 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 r4kcache.h	26.34 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 reboot.h	440 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 reg.h	26 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 regdef.h	2.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rtlx.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seccomp.h	800 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	607 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	884 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📁 sgi	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 sgialib.h	2.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sgiarcs.h	15.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	352 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 sibyte	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 sigcontext.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sim.h	2.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp-cps.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp-ops.h	2.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	3.31 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 sn	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 sni.h	7.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 socket.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sparsemem.h	486 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	459 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	188 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spram.h	262 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackframe.h	10.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackprotector.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	2.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	4.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	3.57 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 termios.h	2.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	6.63 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 time.h	2.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	2.87 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tlb.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbdebug.h	403 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbex.h	788 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	1.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbmisc.h	320 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	619 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	1.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 txx9	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 txx9irq.h	743 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 txx9pio.h	592 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 txx9tmr.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 types.h	487 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	22.2 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 uasm.h	9.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	1.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uprobes.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	3.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	1.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vpe.h	2.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 vr41xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 war.h	7.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 watch.h	827 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 wbflush.h	694 bytes	01/28/2018 09:20:33 PM	rw-r--r--
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Editing: sni.h

/*
 * SNI specific definitions
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1997, 1998 by Ralf Baechle
 * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
 */
#ifndef __ASM_SNI_H
#define __ASM_SNI_H

extern unsigned int sni_brd_type;

#define SNI_BRD_10		   2
#define SNI_BRD_10NEW		   3
#define SNI_BRD_TOWER_OASIC	   4
#define SNI_BRD_MINITOWER	   5
#define SNI_BRD_PCI_TOWER	   6
#define SNI_BRD_RM200		   7
#define SNI_BRD_PCI_MTOWER	   8
#define SNI_BRD_PCI_DESKTOP	   9
#define SNI_BRD_PCI_TOWER_CPLUS	  10
#define SNI_BRD_PCI_MTOWER_CPLUS  11

/* RM400 cpu types */
#define SNI_CPU_M8021		0x01
#define SNI_CPU_M8030		0x04
#define SNI_CPU_M8031		0x06
#define SNI_CPU_M8034		0x0f
#define SNI_CPU_M8037		0x07
#define SNI_CPU_M8040		0x05
#define SNI_CPU_M8043		0x09
#define SNI_CPU_M8050		0x0b
#define SNI_CPU_M8053		0x0d

#define SNI_PORT_BASE		CKSEG1ADDR(0xb4000000)

#ifndef __MIPSEL__
/*
 * ASIC PCI registers for big endian configuration.
 */
#define PCIMT_UCONF		CKSEG1ADDR(0xbfff0004)
#define PCIMT_IOADTIMEOUT2	CKSEG1ADDR(0xbfff000c)
#define PCIMT_IOMEMCONF		CKSEG1ADDR(0xbfff0014)
#define PCIMT_IOMMU		CKSEG1ADDR(0xbfff001c)
#define PCIMT_IOADTIMEOUT1	CKSEG1ADDR(0xbfff0024)
#define PCIMT_DMAACCESS		CKSEG1ADDR(0xbfff002c)
#define PCIMT_DMAHIT		CKSEG1ADDR(0xbfff0034)
#define PCIMT_ERRSTATUS		CKSEG1ADDR(0xbfff003c)
#define PCIMT_ERRADDR		CKSEG1ADDR(0xbfff0044)
#define PCIMT_SYNDROME		CKSEG1ADDR(0xbfff004c)
#define PCIMT_ITPEND		CKSEG1ADDR(0xbfff0054)
#define	 IT_INT2		0x01
#define	 IT_INTD		0x02
#define	 IT_INTC		0x04
#define	 IT_INTB		0x08
#define	 IT_INTA		0x10
#define	 IT_EISA		0x20
#define	 IT_SCSI		0x40
#define	 IT_ETH			0x80
#define PCIMT_IRQSEL		CKSEG1ADDR(0xbfff005c)
#define PCIMT_TESTMEM		CKSEG1ADDR(0xbfff0064)
#define PCIMT_ECCREG		CKSEG1ADDR(0xbfff006c)
#define PCIMT_CONFIG_ADDRESS	CKSEG1ADDR(0xbfff0074)
#define PCIMT_ASIC_ID		CKSEG1ADDR(0xbfff007c)	/* read */
#define PCIMT_SOFT_RESET	CKSEG1ADDR(0xbfff007c)	/* write */
#define PCIMT_PIA_OE		CKSEG1ADDR(0xbfff0084)
#define PCIMT_PIA_DATAOUT	CKSEG1ADDR(0xbfff008c)
#define PCIMT_PIA_DATAIN	CKSEG1ADDR(0xbfff0094)
#define PCIMT_CACHECONF		CKSEG1ADDR(0xbfff009c)
#define PCIMT_INVSPACE		CKSEG1ADDR(0xbfff00a4)
#else
/*
 * ASIC PCI registers for little endian configuration.
 */
#define PCIMT_UCONF		CKSEG1ADDR(0xbfff0000)
#define PCIMT_IOADTIMEOUT2	CKSEG1ADDR(0xbfff0008)
#define PCIMT_IOMEMCONF		CKSEG1ADDR(0xbfff0010)
#define PCIMT_IOMMU		CKSEG1ADDR(0xbfff0018)
#define PCIMT_IOADTIMEOUT1	CKSEG1ADDR(0xbfff0020)
#define PCIMT_DMAACCESS		CKSEG1ADDR(0xbfff0028)
#define PCIMT_DMAHIT		CKSEG1ADDR(0xbfff0030)
#define PCIMT_ERRSTATUS		CKSEG1ADDR(0xbfff0038)
#define PCIMT_ERRADDR		CKSEG1ADDR(0xbfff0040)
#define PCIMT_SYNDROME		CKSEG1ADDR(0xbfff0048)
#define PCIMT_ITPEND		CKSEG1ADDR(0xbfff0050)
#define	 IT_INT2		0x01
#define	 IT_INTD		0x02
#define	 IT_INTC		0x04
#define	 IT_INTB		0x08
#define	 IT_INTA		0x10
#define	 IT_EISA		0x20
#define	 IT_SCSI		0x40
#define	 IT_ETH			0x80
#define PCIMT_IRQSEL		CKSEG1ADDR(0xbfff0058)
#define PCIMT_TESTMEM		CKSEG1ADDR(0xbfff0060)
#define PCIMT_ECCREG		CKSEG1ADDR(0xbfff0068)
#define PCIMT_CONFIG_ADDRESS	CKSEG1ADDR(0xbfff0070)
#define PCIMT_ASIC_ID		CKSEG1ADDR(0xbfff0078)	/* read */
#define PCIMT_SOFT_RESET	CKSEG1ADDR(0xbfff0078)	/* write */
#define PCIMT_PIA_OE		CKSEG1ADDR(0xbfff0080)
#define PCIMT_PIA_DATAOUT	CKSEG1ADDR(0xbfff0088)
#define PCIMT_PIA_DATAIN	CKSEG1ADDR(0xbfff0090)
#define PCIMT_CACHECONF		CKSEG1ADDR(0xbfff0098)
#define PCIMT_INVSPACE		CKSEG1ADDR(0xbfff00a0)
#endif

#define PCIMT_PCI_CONF		CKSEG1ADDR(0xbfff0100)

/*
 * Data port for the PCI bus in IO space
 */
#define PCIMT_CONFIG_DATA	0x0cfc

/*
 * Board specific registers
 */
#define PCIMT_CSMSR		CKSEG1ADDR(0xbfd00000)
#define PCIMT_CSSWITCH		CKSEG1ADDR(0xbfd10000)
#define PCIMT_CSITPEND		CKSEG1ADDR(0xbfd20000)
#define PCIMT_AUTO_PO_EN	CKSEG1ADDR(0xbfd30000)
#define PCIMT_CLR_TEMP		CKSEG1ADDR(0xbfd40000)
#define PCIMT_AUTO_PO_DIS	CKSEG1ADDR(0xbfd50000)
#define PCIMT_EXMSR		CKSEG1ADDR(0xbfd60000)
#define PCIMT_UNUSED1		CKSEG1ADDR(0xbfd70000)
#define PCIMT_CSWCSM		CKSEG1ADDR(0xbfd80000)
#define PCIMT_UNUSED2		CKSEG1ADDR(0xbfd90000)
#define PCIMT_CSLED		CKSEG1ADDR(0xbfda0000)
#define PCIMT_CSMAPISA		CKSEG1ADDR(0xbfdb0000)
#define PCIMT_CSRSTBP		CKSEG1ADDR(0xbfdc0000)
#define PCIMT_CLRPOFF		CKSEG1ADDR(0xbfdd0000)
#define PCIMT_CSTIMER		CKSEG1ADDR(0xbfde0000)
#define PCIMT_PWDN		CKSEG1ADDR(0xbfdf0000)

/*
 * A20R based boards
 */
#define A20R_PT_CLOCK_BASE	CKSEG1ADDR(0xbc040000)
#define A20R_PT_TIM0_ACK	CKSEG1ADDR(0xbc050000)
#define A20R_PT_TIM1_ACK	CKSEG1ADDR(0xbc060000)

#define SNI_A20R_IRQ_BASE	MIPS_CPU_IRQ_BASE
#define SNI_A20R_IRQ_TIMER	(SNI_A20R_IRQ_BASE+5)

#define SNI_PCIT_INT_REG	CKSEG1ADDR(0xbfff000c)

#define SNI_PCIT_INT_START	24
#define SNI_PCIT_INT_END	30

#define PCIT_IRQ_ETHERNET	(MIPS_CPU_IRQ_BASE + 5)
#define PCIT_IRQ_INTA		(SNI_PCIT_INT_START + 0)
#define PCIT_IRQ_INTB		(SNI_PCIT_INT_START + 1)
#define PCIT_IRQ_INTC		(SNI_PCIT_INT_START + 2)
#define PCIT_IRQ_INTD		(SNI_PCIT_INT_START + 3)
#define PCIT_IRQ_SCSI0		(SNI_PCIT_INT_START + 4)
#define PCIT_IRQ_SCSI1		(SNI_PCIT_INT_START + 5)

/*
 * Interrupt 0-16 are EISA interrupts.	Interrupts from 16 on are assigned
 * to the other interrupts generated by ASIC PCI.
 *
 * INT2 is a wired-or of the push button interrupt, high temperature interrupt
 * ASIC PCI interrupt.
 */
#define PCIMT_KEYBOARD_IRQ	 1
#define PCIMT_IRQ_INT2		24
#define PCIMT_IRQ_INTD		25
#define PCIMT_IRQ_INTC		26
#define PCIMT_IRQ_INTB		27
#define PCIMT_IRQ_INTA		28
#define PCIMT_IRQ_EISA		29
#define PCIMT_IRQ_SCSI		30

#define PCIMT_IRQ_ETHERNET	(MIPS_CPU_IRQ_BASE+6)

#if 0
#define PCIMT_IRQ_TEMPERATURE	24
#define PCIMT_IRQ_EISA_NMI	25
#define PCIMT_IRQ_POWER_OFF	26
#define PCIMT_IRQ_BUTTON	27
#endif

/*
 * Base address for the mapped 16mb EISA bus segment.
 */
#define PCIMT_EISA_BASE		CKSEG1ADDR(0xb0000000)

/* PCI EISA Interrupt acknowledge  */
#define PCIMT_INT_ACKNOWLEDGE	CKSEG1ADDR(0xba000000)

/*
 *  SNI ID PROM
 *
 * SNI_IDPROM_MEMSIZE  Memsize in 16MB quantities
 * SNI_IDPROM_BRDTYPE  Board Type
 * SNI_IDPROM_CPUTYPE  CPU Type on RM400
 */
#ifdef CONFIG_CPU_BIG_ENDIAN
#define __SNI_END 0
#endif
#ifdef CONFIG_CPU_LITTLE_ENDIAN
#define __SNI_END 3
#endif
#define SNI_IDPROM_BASE	       CKSEG1ADDR(0x1ff00000)
#define SNI_IDPROM_MEMSIZE     (SNI_IDPROM_BASE + (0x28 ^ __SNI_END))
#define SNI_IDPROM_BRDTYPE     (SNI_IDPROM_BASE + (0x29 ^ __SNI_END))
#define SNI_IDPROM_CPUTYPE     (SNI_IDPROM_BASE + (0x30 ^ __SNI_END))

#define SNI_IDPROM_SIZE 0x1000

/* board specific init functions */
extern void sni_a20r_init(void);
extern void sni_pcit_init(void);
extern void sni_rm200_init(void);
extern void sni_pcimt_init(void);

/* board specific irq init functions */
extern void sni_a20r_irq_init(void);
extern void sni_pcit_irq_init(void);
extern void sni_pcit_cplus_irq_init(void);
extern void sni_rm200_irq_init(void);
extern void sni_pcimt_irq_init(void);

/* timer inits */
extern void sni_cpu_time_init(void);

/* eisa init for RM200/400 */
#ifdef CONFIG_EISA
extern int sni_eisa_root_init(void);
#else
static inline int sni_eisa_root_init(void)
{
	return 0;
}
#endif

/* common irq stuff */
extern void (*sni_hwint)(void);
extern struct irqaction sni_isa_irq;

#endif /* __ASM_SNI_H */