OXIESEC PANEL
- Current Dir:
/
/
usr
/
src
/
linux-headers-4.15.0-213
/
arch
/
mips
/
include
/
asm
Server IP: 139.59.38.164
Upload:
Create Dir:
Name
Size
Modified
Perms
📁
..
-
05/09/2024 07:14:13 AM
rwxr-xr-x
📄
Kbuild
577 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
abi.h
853 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
addrspace.h
4.1 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
amon.h
409 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
arch_hweight.h
792 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
asm-eva.h
6.82 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
asm-offsets.h
35 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
asm-prototypes.h
197 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
asm.h
8.47 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
asmmacro-32.h
2.47 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
asmmacro-64.h
1.22 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
asmmacro.h
14.07 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
atomic.h
19.73 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
barrier.h
8.03 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bcache.h
2.04 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bitops.h
15.46 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bitrev.h
608 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
bmips-spaces.h
268 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
bmips.h
3.45 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
bootinfo.h
5.08 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
branch.h
2.35 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
break.h
787 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
bug.h
759 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
bugs.h
944 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
cache.h
546 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
cacheflush.h
4.99 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cacheops.h
3.71 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cdmm.h
3.67 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cevt-r4k.h
823 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
checksum.h
6.43 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
clock.h
997 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
clocksource.h
884 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
cmp.h
492 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
cmpxchg.h
5.28 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
compat-signal.h
640 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
compat.h
6.66 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
compiler.h
2.96 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
cop2.h
1.77 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cpu-features.h
19.46 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
cpu-info.h
5.84 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
cpu-type.h
4.13 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
cpu.h
15.54 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
cpufeature.h
717 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
debug.h
654 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📁
dec
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
delay.h
841 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
device.h
347 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
div64.h
2.17 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
dma-coherence.h
813 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
dma-mapping.h
981 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
dma.h
9.92 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ds1287.h
1019 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
dsemul.h
3.24 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
dsp.h
1.91 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
edac.h
819 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
elf.h
15.04 KB
01/28/2018 09:20:33 PM
rw-r--r--
📁
emma
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
errno.h
429 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
eva.h
796 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
exec.h
579 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
extable.h
241 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
fb.h
372 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
fixmap.h
2.29 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
floppy.h
1.57 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
fpregdef.h
2.66 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
fpu.h
5.21 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
fpu_emulator.h
5.74 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ftrace.h
2.11 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
futex.h
4.87 KB
01/28/2018 09:20:33 PM
rw-r--r--
📁
fw
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
gio_device.h
1.5 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
gt64120.h
19.37 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
hardirq.h
544 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
hazards.h
8.36 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
highmem.h
1.72 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
hpet.h
1.93 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
hugetlb.h
2.76 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
hw_irq.h
475 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
i8259.h
2.52 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ide.h
330 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
idle.h
689 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
inst.h
2.34 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
io.h
18.44 KB
06/16/2023 05:32:39 PM
rw-r--r--
📁
ip32
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
irq.h
2.26 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
irq_cpu.h
708 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
irq_gt641xx.h
2.69 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
irq_regs.h
744 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
irqflags.h
4.04 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
isa-rev.h
556 bytes
06/16/2023 05:32:39 PM
rw-r--r--
📄
isadep.h
603 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
jazz.h
8 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
jazzdma.h
2.97 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
jump_label.h
1.4 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
kdebug.h
303 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
kexec.h
1.53 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
kgdb.h
1.19 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
kmap_types.h
221 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
kprobes.h
2.68 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
kvm_host.h
37.88 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
kvm_para.h
2.09 KB
01/28/2018 09:20:33 PM
rw-r--r--
📁
lasat
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
linkage.h
306 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
llsc.h
623 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
local.h
4.99 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
m48t37.h
732 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
maar.h
4.04 KB
01/28/2018 09:20:33 PM
rw-r--r--
📁
mach-ar7
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-ath25
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-ath79
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-au1x00
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-bcm47xx
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-bcm63xx
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-bmips
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-cavium-octeon
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-cobalt
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-db1x00
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-dec
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-emma2rh
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-generic
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-ip22
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-ip27
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-ip28
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-ip32
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-jazz
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-jz4740
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-lantiq
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-lasat
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-loongson32
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-loongson64
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-malta
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-netlogic
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-paravirt
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-pic32
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-pistachio
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-pmcs-msp71xx
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-pnx833x
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-ralink
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-rc32434
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-rm
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-sibyte
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-tx39xx
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-tx49xx
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-vr41xx
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mach-xilfpga
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
machine.h
2.93 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
mc146818-time.h
3.69 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mc146818rtc.h
450 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📁
mips-boards
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
mips-cm.h
15.86 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
mips-cpc.h
5.83 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mips-cps.h
6.55 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mips-gic.h
12.3 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
mips-r2-to-r6-emul.h
2.05 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mips_machine.h
1.32 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mips_mt.h
707 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
mipsmtregs.h
10.9 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mipsprom.h
2.1 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mipsregs.h
88.1 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
mmu.h
550 bytes
06/16/2023 05:32:39 PM
rw-r--r--
📄
mmu_context.h
5.41 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
mmzone.h
561 bytes
06/16/2023 05:32:39 PM
rw-r--r--
📄
module.h
4.45 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
msa.h
8.01 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
msc01_ic.h
6.55 KB
01/28/2018 09:20:33 PM
rw-r--r--
📁
netlogic
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
nile4.h
10.33 KB
01/28/2018 09:20:33 PM
rw-r--r--
📁
octeon
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
paccess.h
3.07 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
page.h
7.19 KB
01/28/2018 09:20:33 PM
rw-r--r--
📁
pci
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
pci.h
4.08 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
perf_event.h
482 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
pgalloc.h
3.21 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
pgtable-32.h
7.31 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
pgtable-64.h
10.87 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
pgtable-bits.h
7.36 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
pgtable.h
17.34 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
pm-cps.h
1.68 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
pm.h
3.99 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
pmon.h
1.64 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
prefetch.h
2.1 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
processor.h
11.71 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
prom.h
845 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
ptrace.h
5.55 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
r4k-timer.h
604 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
r4kcache.h
26.34 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
reboot.h
440 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
reg.h
26 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
regdef.h
2.63 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
rtlx.h
2.1 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
seccomp.h
800 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
serial.h
607 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
setup.h
884 bytes
06/16/2023 05:32:39 PM
rw-r--r--
📁
sgi
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
sgialib.h
2.45 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
sgiarcs.h
15.32 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
shmparam.h
352 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📁
sibyte
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
sigcontext.h
1.04 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
signal.h
1.02 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
sim.h
2.32 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
smp-cps.h
1.18 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
smp-ops.h
2.33 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
smp.h
3.31 KB
06/16/2023 05:32:39 PM
rw-r--r--
📁
sn
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
sni.h
7.27 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
socket.h
1.34 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
sparsemem.h
486 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
spinlock.h
459 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
spinlock_types.h
188 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
spram.h
262 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
stackframe.h
10.82 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
stackprotector.h
1.15 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
stacktrace.h
2.15 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
string.h
2.94 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
switch_to.h
4.19 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
syscall.h
3.57 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
termios.h
2.89 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
thread_info.h
6.63 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
time.h
2.13 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
timex.h
2.87 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
tlb.h
1.09 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tlbdebug.h
403 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
tlbex.h
788 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
tlbflush.h
1.67 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tlbmisc.h
320 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
topology.h
619 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
traps.h
1.25 KB
01/28/2018 09:20:33 PM
rw-r--r--
📁
txx9
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
txx9irq.h
743 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
txx9pio.h
592 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
txx9tmr.h
1.59 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
types.h
487 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
uaccess.h
22.2 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
uasm.h
9.18 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
unistd.h
1.9 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
uprobes.h
1.11 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
vdso.h
3.72 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
vga.h
1.26 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
vpe.h
2.7 KB
01/28/2018 09:20:33 PM
rw-r--r--
📁
vr41xx
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
war.h
7.48 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
watch.h
827 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
wbflush.h
694 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📁
xtalk
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
yamon-dt.h
1.88 KB
01/28/2018 09:20:33 PM
rw-r--r--
Editing: pgtable-bits.h
Close
/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1994 - 2002 by Ralf Baechle * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. * Copyright (C) 2002 Maciej W. Rozycki */ #ifndef _ASM_PGTABLE_BITS_H #define _ASM_PGTABLE_BITS_H /* * Note that we shift the lower 32bits of each EntryLo[01] entry * 6 bits to the left. That way we can convert the PFN into the * physical address by a single 'and' operation and gain 6 additional * bits for storing information which isn't present in a normal * MIPS page table. * * Similar to the Alpha port, we need to keep track of the ref * and mod bits in software. We have a software "yeah you can read * from this page" bit, and a hardware one which actually lets the * process read from the page. On the same token we have a software * writable bit and the real hardware one which actually lets the * process write to the page, this keeps a mod bit via the hardware * dirty bit. * * Certain revisions of the R4000 and R5000 have a bug where if a * certain sequence occurs in the last 3 instructions of an executable * page, and the following page is not mapped, the cpu can do * unpredictable things. The code (when it is written) to deal with * this problem will be in the update_mmu_cache() code for the r4k. */ #if defined(CONFIG_XPA) /* * Page table bit offsets used for 64 bit physical addressing on * MIPS32r5 with XPA. */ enum pgtable_bits { /* Used by TLB hardware (placed in EntryLo*) */ _PAGE_NO_EXEC_SHIFT, _PAGE_NO_READ_SHIFT, _PAGE_GLOBAL_SHIFT, _PAGE_VALID_SHIFT, _PAGE_DIRTY_SHIFT, _CACHE_SHIFT, /* Used only by software (masked out before writing EntryLo*) */ _PAGE_PRESENT_SHIFT = 24, _PAGE_WRITE_SHIFT, _PAGE_ACCESSED_SHIFT, _PAGE_MODIFIED_SHIFT, }; /* * Bits for extended EntryLo0/EntryLo1 registers */ #define _PFNX_MASK 0xffffff #elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) /* * Page table bit offsets used for 36 bit physical addressing on MIPS32, * for example with Alchemy or Netlogic XLP/XLR. */ enum pgtable_bits { /* Used by TLB hardware (placed in EntryLo*) */ _PAGE_GLOBAL_SHIFT, _PAGE_VALID_SHIFT, _PAGE_DIRTY_SHIFT, _CACHE_SHIFT, /* Used only by software (masked out before writing EntryLo*) */ _PAGE_PRESENT_SHIFT = _CACHE_SHIFT + 3, _PAGE_NO_READ_SHIFT, _PAGE_WRITE_SHIFT, _PAGE_ACCESSED_SHIFT, _PAGE_MODIFIED_SHIFT, }; #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) /* Page table bits used for r3k systems */ enum pgtable_bits { /* Used only by software (writes to EntryLo ignored) */ _PAGE_PRESENT_SHIFT, _PAGE_NO_READ_SHIFT, _PAGE_WRITE_SHIFT, _PAGE_ACCESSED_SHIFT, _PAGE_MODIFIED_SHIFT, /* Used by TLB hardware (placed in EntryLo) */ _PAGE_GLOBAL_SHIFT = 8, _PAGE_VALID_SHIFT, _PAGE_DIRTY_SHIFT, _CACHE_UNCACHED_SHIFT, }; #else /* Page table bits used for r4k systems */ enum pgtable_bits { /* Used only by software (masked out before writing EntryLo*) */ _PAGE_PRESENT_SHIFT, #if !defined(CONFIG_CPU_HAS_RIXI) _PAGE_NO_READ_SHIFT, #endif _PAGE_WRITE_SHIFT, _PAGE_ACCESSED_SHIFT, _PAGE_MODIFIED_SHIFT, #if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) _PAGE_HUGE_SHIFT, #endif /* Used by TLB hardware (placed in EntryLo*) */ #if defined(CONFIG_CPU_HAS_RIXI) _PAGE_NO_EXEC_SHIFT, _PAGE_NO_READ_SHIFT, #endif _PAGE_GLOBAL_SHIFT, _PAGE_VALID_SHIFT, _PAGE_DIRTY_SHIFT, _CACHE_SHIFT, }; #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */ /* Used only by software */ #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) #if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) # define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) #endif /* Used by TLB hardware (placed in EntryLo*) */ #if defined(CONFIG_XPA) # define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT) #elif defined(CONFIG_CPU_HAS_RIXI) # define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0) #endif #define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT) #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) # define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT) # define _CACHE_MASK _CACHE_UNCACHED # define _PFN_SHIFT PAGE_SHIFT #else # define _CACHE_MASK (7 << _CACHE_SHIFT) # define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) #endif #ifndef _PAGE_NO_EXEC #define _PAGE_NO_EXEC 0 #endif #define _PAGE_SILENT_READ _PAGE_VALID #define _PAGE_SILENT_WRITE _PAGE_DIRTY #define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) /* * The final layouts of the PTE bits are: * * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P * 32-bit, R1 or earler: CCC D V G M A W R P * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P * 32-bit, R2 or later: CCC D V G RI/R XI M A W P */ /* * pte_to_entrylo converts a page table entry (PTE) into a Mips * entrylo0/1 value. */ static inline uint64_t pte_to_entrylo(unsigned long pte_val) { #ifdef CONFIG_CPU_HAS_RIXI if (cpu_has_rixi) { int sa; #ifdef CONFIG_32BIT sa = 31 - _PAGE_NO_READ_SHIFT; #else sa = 63 - _PAGE_NO_READ_SHIFT; #endif /* * C has no way to express that this is a DSRL * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily * in the fast path this is done in assembly */ return (pte_val >> _PAGE_GLOBAL_SHIFT) | ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa); } #endif return pte_val >> _PAGE_GLOBAL_SHIFT; } /* * Cache attributes */ #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) #define _CACHE_CACHABLE_NONCOHERENT 0 #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED #elif defined(CONFIG_CPU_SB1) /* No penalty for being coherent on the SB1, so just use it for "noncoherent" spaces, too. Shouldn't hurt. */ #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) #elif defined(CONFIG_CPU_LOONGSON3) /* Using COHERENT flag for NONCOHERENT doesn't hurt. */ #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ #define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ #elif defined(CONFIG_MACH_INGENIC) /* Ingenic uses the WA bit to achieve write-combine memory writes */ #define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT) #endif #ifndef _CACHE_CACHABLE_NO_WA #define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) #endif #ifndef _CACHE_CACHABLE_WA #define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) #endif #ifndef _CACHE_UNCACHED #define _CACHE_UNCACHED (2<<_CACHE_SHIFT) #endif #ifndef _CACHE_CACHABLE_NONCOHERENT #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) #endif #ifndef _CACHE_CACHABLE_CE #define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) #endif #ifndef _CACHE_CACHABLE_COW #define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) #endif #ifndef _CACHE_CACHABLE_CUW #define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) #endif #ifndef _CACHE_UNCACHED_ACCELERATED #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) #endif #define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED) #define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED) #define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \ _PFN_MASK | _CACHE_MASK) #endif /* _ASM_PGTABLE_BITS_H */