OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:13 AM	rwxr-xr-x
📄 Kbuild	577 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 abi.h	853 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 addrspace.h	4.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amon.h	409 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 arch_hweight.h	792 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-eva.h	6.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	197 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm.h	8.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro-32.h	2.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro-64.h	1.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro.h	14.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	19.73 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 barrier.h	8.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcache.h	2.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	15.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitrev.h	608 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bmips-spaces.h	268 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bmips.h	3.45 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 bootinfo.h	5.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 branch.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 break.h	787 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	759 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	944 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	546 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	4.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheops.h	3.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cdmm.h	3.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cevt-r4k.h	823 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	6.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clock.h	997 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 clocksource.h	884 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmp.h	492 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	5.28 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compat-signal.h	640 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat.h	6.66 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compiler.h	2.96 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cop2.h	1.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu-features.h	19.46 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpu-info.h	5.84 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpu-type.h	4.13 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpu.h	15.54 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpufeature.h	717 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 debug.h	654 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 dec	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 delay.h	841 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 device.h	347 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 div64.h	2.17 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 dma-coherence.h	813 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	981 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	9.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ds1287.h	1019 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dsemul.h	3.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dsp.h	1.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 edac.h	819 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	15.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 emma	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 errno.h	429 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 eva.h	796 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 exec.h	579 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable.h	241 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	372 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpregdef.h	2.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu.h	5.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu_emulator.h	5.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	2.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	4.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 fw	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 gio_device.h	1.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gt64120.h	19.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	544 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hazards.h	8.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	1.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hpet.h	1.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb.h	2.76 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hw_irq.h	475 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 i8259.h	2.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	330 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 idle.h	689 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 inst.h	2.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	18.44 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 ip32	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 irq.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_cpu.h	708 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_gt641xx.h	2.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_regs.h	744 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	4.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 isa-rev.h	556 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 isadep.h	603 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 jazz.h	8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jazzdma.h	2.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	1.4 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kdebug.h	303 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	1.53 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kgdb.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	221 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_host.h	37.88 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_para.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 lasat	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 linkage.h	306 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 llsc.h	623 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 local.h	4.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m48t37.h	732 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 maar.h	4.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 mach-ar7	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ath25	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ath79	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-au1x00	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-bcm47xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-bcm63xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-bmips	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-cavium-octeon	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-cobalt	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-db1x00	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-dec	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-emma2rh	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-generic	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ip22	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ip27	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ip28	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ip32	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-jazz	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-jz4740	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-lantiq	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-lasat	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-loongson32	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-loongson64	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-malta	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-netlogic	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-paravirt	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-pic32	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-pistachio	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-pmcs-msp71xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-pnx833x	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ralink	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-rc32434	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-rm	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-sibyte	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-tx39xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-tx49xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-vr41xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-xilfpga	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 machine.h	2.93 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mc146818-time.h	3.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc.h	450 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 mips-boards	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 mips-cm.h	15.86 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mips-cpc.h	5.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips-cps.h	6.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips-gic.h	12.3 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mips-r2-to-r6-emul.h	2.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips_machine.h	1.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips_mt.h	707 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mipsmtregs.h	10.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mipsprom.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mipsregs.h	88.1 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmu.h	550 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmu_context.h	5.41 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmzone.h	561 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 module.h	4.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msa.h	8.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msc01_ic.h	6.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 netlogic	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 nile4.h	10.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 octeon	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 paccess.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	7.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 pci	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 pci.h	4.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	482 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	3.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-32.h	7.31 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtable-64.h	10.87 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtable-bits.h	7.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	17.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm-cps.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm.h	3.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmon.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 prefetch.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	11.71 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 prom.h	845 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	5.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 r4k-timer.h	604 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 r4kcache.h	26.34 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 reboot.h	440 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 reg.h	26 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 regdef.h	2.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rtlx.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seccomp.h	800 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	607 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	884 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📁 sgi	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 sgialib.h	2.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sgiarcs.h	15.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	352 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 sibyte	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 sigcontext.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sim.h	2.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp-cps.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp-ops.h	2.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	3.31 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 sn	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 sni.h	7.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 socket.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sparsemem.h	486 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	459 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	188 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spram.h	262 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackframe.h	10.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackprotector.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	2.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	4.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	3.57 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 termios.h	2.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	6.63 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 time.h	2.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	2.87 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tlb.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbdebug.h	403 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbex.h	788 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	1.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbmisc.h	320 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	619 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	1.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 txx9	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 txx9irq.h	743 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 txx9pio.h	592 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 txx9tmr.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 types.h	487 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	22.2 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 uasm.h	9.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	1.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uprobes.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	3.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	1.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vpe.h	2.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 vr41xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 war.h	7.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 watch.h	827 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 wbflush.h	694 bytes	01/28/2018 09:20:33 PM	rw-r--r--
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Editing: mips-gic.h

/*
 * Copyright (C) 2017 Imagination Technologies
 * Author: Paul Burton <paul.burton@mips.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#ifndef __MIPS_ASM_MIPS_CPS_H__
# error Please include asm/mips-cps.h rather than asm/mips-gic.h
#endif

#ifndef __MIPS_ASM_MIPS_GIC_H__
#define __MIPS_ASM_MIPS_GIC_H__

#include <linux/bitops.h>

/* The base address of the GIC registers */
extern void __iomem *mips_gic_base;

/* Offsets from the GIC base address to various control blocks */
#define MIPS_GIC_SHARED_OFS	0x00000
#define MIPS_GIC_SHARED_SZ	0x08000
#define MIPS_GIC_LOCAL_OFS	0x08000
#define MIPS_GIC_LOCAL_SZ	0x04000
#define MIPS_GIC_REDIR_OFS	0x0c000
#define MIPS_GIC_REDIR_SZ	0x04000
#define MIPS_GIC_USER_OFS	0x10000
#define MIPS_GIC_USER_SZ	0x10000

/* For read-only shared registers */
#define GIC_ACCESSOR_RO(sz, off, name)					\
	CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name)

/* For read-write shared registers */
#define GIC_ACCESSOR_RW(sz, off, name)					\
	CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name)

/* For read-only local registers */
#define GIC_VX_ACCESSOR_RO(sz, off, name)				\
	CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name)	\
	CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)

/* For read-write local registers */
#define GIC_VX_ACCESSOR_RW(sz, off, name)				\
	CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name)	\
	CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)

/* For read-only shared per-interrupt registers */
#define GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name)			\
static inline void __iomem *addr_gic_##name(unsigned int intr)		\
{									\
	return mips_gic_base + (off) + (intr * (stride));		\
}									\
									\
static inline unsigned int read_gic_##name(unsigned int intr)		\
{									\
	BUILD_BUG_ON(sz != 32);						\
	return __raw_readl(addr_gic_##name(intr));			\
}

/* For read-write shared per-interrupt registers */
#define GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name)			\
	GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name)			\
									\
static inline void write_gic_##name(unsigned int intr,			\
				    unsigned int val)			\
{									\
	BUILD_BUG_ON(sz != 32);						\
	__raw_writel(val, addr_gic_##name(intr));			\
}

/* For read-only local per-interrupt registers */
#define GIC_VX_ACCESSOR_RO_INTR_REG(sz, off, stride, name)		\
	GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off,		\
				 stride, vl_##name)			\
	GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off,		\
				 stride, vo_##name)

/* For read-write local per-interrupt registers */
#define GIC_VX_ACCESSOR_RW_INTR_REG(sz, off, stride, name)		\
	GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off,		\
				 stride, vl_##name)			\
	GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off,		\
				 stride, vo_##name)

/* For read-only shared bit-per-interrupt registers */
#define GIC_ACCESSOR_RO_INTR_BIT(off, name)				\
static inline void __iomem *addr_gic_##name(void)			\
{									\
	return mips_gic_base + (off);					\
}									\
									\
static inline unsigned int read_gic_##name(unsigned int intr)		\
{									\
	void __iomem *addr = addr_gic_##name();				\
	unsigned int val;						\
									\
	if (mips_cm_is64) {						\
		addr += (intr / 64) * sizeof(uint64_t);			\
		val = __raw_readq(addr) >> intr % 64;			\
	} else {							\
		addr += (intr / 32) * sizeof(uint32_t);			\
		val = __raw_readl(addr) >> intr % 32;			\
	}								\
									\
	return val & 0x1;						\
}

/* For read-write shared bit-per-interrupt registers */
#define GIC_ACCESSOR_RW_INTR_BIT(off, name)				\
	GIC_ACCESSOR_RO_INTR_BIT(off, name)				\
									\
static inline void write_gic_##name(unsigned int intr)			\
{									\
	void __iomem *addr = addr_gic_##name();				\
									\
	if (mips_cm_is64) {						\
		addr += (intr / 64) * sizeof(uint64_t);			\
		__raw_writeq(BIT(intr % 64), addr);			\
	} else {							\
		addr += (intr / 32) * sizeof(uint32_t);			\
		__raw_writel(BIT(intr % 32), addr);			\
	}								\
}									\
									\
static inline void change_gic_##name(unsigned int intr,			\
				     unsigned int val)			\
{									\
	void __iomem *addr = addr_gic_##name();				\
									\
	if (mips_cm_is64) {						\
		uint64_t _val;						\
									\
		addr += (intr / 64) * sizeof(uint64_t);			\
		_val = __raw_readq(addr);				\
		_val &= ~BIT_ULL(intr % 64);				\
		_val |= (uint64_t)val << (intr % 64);			\
		__raw_writeq(_val, addr);				\
	} else {							\
		uint32_t _val;						\
									\
		addr += (intr / 32) * sizeof(uint32_t);			\
		_val = __raw_readl(addr);				\
		_val &= ~BIT(intr % 32);				\
		_val |= val << (intr % 32);				\
		__raw_writel(_val, addr);				\
	}								\
}

/* For read-only local bit-per-interrupt registers */
#define GIC_VX_ACCESSOR_RO_INTR_BIT(sz, off, name)			\
	GIC_ACCESSOR_RO_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off,		\
				 vl_##name)				\
	GIC_ACCESSOR_RO_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off,		\
				 vo_##name)

/* For read-write local bit-per-interrupt registers */
#define GIC_VX_ACCESSOR_RW_INTR_BIT(sz, off, name)			\
	GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off,		\
				 vl_##name)				\
	GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off,		\
				 vo_##name)

/* GIC_SH_CONFIG - Information about the GIC configuration */
GIC_ACCESSOR_RW(32, 0x000, config)
#define GIC_CONFIG_COUNTSTOP		BIT(28)
#define GIC_CONFIG_COUNTBITS		GENMASK(27, 24)
#define GIC_CONFIG_NUMINTERRUPTS	GENMASK(23, 16)
#define GIC_CONFIG_PVPS			GENMASK(6, 0)

/* GIC_SH_COUNTER - Shared global counter value */
GIC_ACCESSOR_RW(64, 0x010, counter)
GIC_ACCESSOR_RW(32, 0x010, counter_32l)
GIC_ACCESSOR_RW(32, 0x014, counter_32h)

/* GIC_SH_POL_* - Configures interrupt polarity */
GIC_ACCESSOR_RW_INTR_BIT(0x100, pol)
#define GIC_POL_ACTIVE_LOW		0	/* when level triggered */
#define GIC_POL_ACTIVE_HIGH		1	/* when level triggered */
#define GIC_POL_FALLING_EDGE		0	/* when single-edge triggered */
#define GIC_POL_RISING_EDGE		1	/* when single-edge triggered */

/* GIC_SH_TRIG_* - Configures interrupts to be edge or level triggered */
GIC_ACCESSOR_RW_INTR_BIT(0x180, trig)
#define GIC_TRIG_LEVEL			0
#define GIC_TRIG_EDGE			1

/* GIC_SH_DUAL_* - Configures whether interrupts trigger on both edges */
GIC_ACCESSOR_RW_INTR_BIT(0x200, dual)
#define GIC_DUAL_SINGLE			0	/* when edge-triggered */
#define GIC_DUAL_DUAL			1	/* when edge-triggered */

/* GIC_SH_WEDGE - Write an 'edge', ie. trigger an interrupt */
GIC_ACCESSOR_RW(32, 0x280, wedge)
#define GIC_WEDGE_RW			BIT(31)
#define GIC_WEDGE_INTR			GENMASK(7, 0)

/* GIC_SH_RMASK_* - Reset/clear shared interrupt mask bits */
GIC_ACCESSOR_RW_INTR_BIT(0x300, rmask)

/* GIC_SH_SMASK_* - Set shared interrupt mask bits */
GIC_ACCESSOR_RW_INTR_BIT(0x380, smask)

/* GIC_SH_MASK_* - Read the current shared interrupt mask */
GIC_ACCESSOR_RO_INTR_BIT(0x400, mask)

/* GIC_SH_PEND_* - Read currently pending shared interrupts */
GIC_ACCESSOR_RO_INTR_BIT(0x480, pend)

/* GIC_SH_MAPx_PIN - Map shared interrupts to a particular CPU pin */
GIC_ACCESSOR_RW_INTR_REG(32, 0x500, 0x4, map_pin)
#define GIC_MAP_PIN_MAP_TO_PIN		BIT(31)
#define GIC_MAP_PIN_MAP_TO_NMI		BIT(30)
#define GIC_MAP_PIN_MAP			GENMASK(5, 0)

/* GIC_SH_MAPx_VP - Map shared interrupts to a particular Virtual Processor */
GIC_ACCESSOR_RW_INTR_REG(32, 0x2000, 0x20, map_vp)

/* GIC_Vx_CTL - VP-level interrupt control */
GIC_VX_ACCESSOR_RW(32, 0x000, ctl)
#define GIC_VX_CTL_FDC_ROUTABLE		BIT(4)
#define GIC_VX_CTL_SWINT_ROUTABLE	BIT(3)
#define GIC_VX_CTL_PERFCNT_ROUTABLE	BIT(2)
#define GIC_VX_CTL_TIMER_ROUTABLE	BIT(1)
#define GIC_VX_CTL_EIC			BIT(0)

/* GIC_Vx_PEND - Read currently pending local interrupts */
GIC_VX_ACCESSOR_RO(32, 0x004, pend)

/* GIC_Vx_MASK - Read the current local interrupt mask */
GIC_VX_ACCESSOR_RO(32, 0x008, mask)

/* GIC_Vx_RMASK - Reset/clear local interrupt mask bits */
GIC_VX_ACCESSOR_RW(32, 0x00c, rmask)

/* GIC_Vx_SMASK - Set local interrupt mask bits */
GIC_VX_ACCESSOR_RW(32, 0x010, smask)

/* GIC_Vx_*_MAP - Route local interrupts to the desired pins */
GIC_VX_ACCESSOR_RW_INTR_REG(32, 0x040, 0x4, map)

/* GIC_Vx_WD_MAP - Route the local watchdog timer interrupt */
GIC_VX_ACCESSOR_RW(32, 0x040, wd_map)

/* GIC_Vx_COMPARE_MAP - Route the local count/compare interrupt */
GIC_VX_ACCESSOR_RW(32, 0x044, compare_map)

/* GIC_Vx_TIMER_MAP - Route the local CPU timer (cp0 count/compare) interrupt */
GIC_VX_ACCESSOR_RW(32, 0x048, timer_map)

/* GIC_Vx_FDC_MAP - Route the local fast debug channel interrupt */
GIC_VX_ACCESSOR_RW(32, 0x04c, fdc_map)

/* GIC_Vx_PERFCTR_MAP - Route the local performance counter interrupt */
GIC_VX_ACCESSOR_RW(32, 0x050, perfctr_map)

/* GIC_Vx_SWINT0_MAP - Route the local software interrupt 0 */
GIC_VX_ACCESSOR_RW(32, 0x054, swint0_map)

/* GIC_Vx_SWINT1_MAP - Route the local software interrupt 1 */
GIC_VX_ACCESSOR_RW(32, 0x058, swint1_map)

/* GIC_Vx_OTHER - Configure access to other Virtual Processor registers */
GIC_VX_ACCESSOR_RW(32, 0x080, other)
#define GIC_VX_OTHER_VPNUM		GENMASK(5, 0)

/* GIC_Vx_IDENT - Retrieve the local Virtual Processor's ID */
GIC_VX_ACCESSOR_RO(32, 0x088, ident)
#define GIC_VX_IDENT_VPNUM		GENMASK(5, 0)

/* GIC_Vx_COMPARE - Value to compare with GIC_SH_COUNTER */
GIC_VX_ACCESSOR_RW(64, 0x0a0, compare)

/* GIC_Vx_EIC_SHADOW_SET_BASE - Set shadow register set for each interrupt */
GIC_VX_ACCESSOR_RW_INTR_REG(32, 0x100, 0x4, eic_shadow_set)

/**
 * enum mips_gic_local_interrupt - GIC local interrupts
 * @GIC_LOCAL_INT_WD: GIC watchdog timer interrupt
 * @GIC_LOCAL_INT_COMPARE: GIC count/compare interrupt
 * @GIC_LOCAL_INT_TIMER: CP0 count/compare interrupt
 * @GIC_LOCAL_INT_PERFCTR: Performance counter interrupt
 * @GIC_LOCAL_INT_SWINT0: Software interrupt 0
 * @GIC_LOCAL_INT_SWINT1: Software interrupt 1
 * @GIC_LOCAL_INT_FDC: Fast debug channel interrupt
 * @GIC_NUM_LOCAL_INTRS: The number of local interrupts
 *
 * Enumerates interrupts provided by the GIC that are local to a VP.
 */
enum mips_gic_local_interrupt {
	GIC_LOCAL_INT_WD,
	GIC_LOCAL_INT_COMPARE,
	GIC_LOCAL_INT_TIMER,
	GIC_LOCAL_INT_PERFCTR,
	GIC_LOCAL_INT_SWINT0,
	GIC_LOCAL_INT_SWINT1,
	GIC_LOCAL_INT_FDC,
	GIC_NUM_LOCAL_INTRS
};

/**
 * mips_gic_present() - Determine whether a GIC is present
 *
 * Determines whether a MIPS Global Interrupt Controller (GIC) is present in
 * the system that the kernel is running on.
 *
 * Return true if a GIC is present, else false.
 */
static inline bool mips_gic_present(void)
{
	return IS_ENABLED(CONFIG_MIPS_GIC) && mips_gic_base;
}

/**
 * mips_gic_vx_map_reg() - Return GIC_Vx_<intr>_MAP register offset
 * @intr: A GIC local interrupt
 *
 * Determine the index of the GIC_VL_<intr>_MAP or GIC_VO_<intr>_MAP register
 * within the block of GIC map registers. This is almost the same as the order
 * of interrupts in the pending & mask registers, as used by enum
 * mips_gic_local_interrupt, but moves the FDC interrupt & thus offsets the
 * interrupts after it...
 *
 * Return: The map register index corresponding to @intr.
 *
 * The return value is suitable for use with the (read|write)_gic_v[lo]_map
 * accessor functions.
 */
static inline unsigned int
mips_gic_vx_map_reg(enum mips_gic_local_interrupt intr)
{
	/* WD, Compare & Timer are 1:1 */
	if (intr <= GIC_LOCAL_INT_TIMER)
		return intr;

/* FDC moves to after Timer... */
	if (intr == GIC_LOCAL_INT_FDC)
		return GIC_LOCAL_INT_TIMER + 1;

/* As a result everything else is offset by 1 */
	return intr + 1;
}

/**
 * gic_get_c0_compare_int() - Return cp0 count/compare interrupt virq
 *
 * Determine the virq number to use for the coprocessor 0 count/compare
 * interrupt, which may be routed via the GIC.
 *
 * Returns the virq number or a negative error number.
 */
extern int gic_get_c0_compare_int(void);

/**
 * gic_get_c0_perfcount_int() - Return performance counter interrupt virq
 *
 * Determine the virq number to use for CPU performance counter interrupts,
 * which may be routed via the GIC.
 *
 * Returns the virq number or a negative error number.
 */
extern int gic_get_c0_perfcount_int(void);

/**
 * gic_get_c0_fdc_int() - Return fast debug channel interrupt virq
 *
 * Determine the virq number to use for fast debug channel (FDC) interrupts,
 * which may be routed via the GIC.
 *
 * Returns the virq number or a negative error number.
 */
extern int gic_get_c0_fdc_int(void);

#endif /* __MIPS_ASM_MIPS_CPS_H__ */