OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:13 AM	rwxr-xr-x
📄 Kbuild	577 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 abi.h	853 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 addrspace.h	4.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amon.h	409 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 arch_hweight.h	792 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-eva.h	6.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	197 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm.h	8.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro-32.h	2.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro-64.h	1.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro.h	14.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	19.73 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 barrier.h	8.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcache.h	2.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	15.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitrev.h	608 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bmips-spaces.h	268 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bmips.h	3.45 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 bootinfo.h	5.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 branch.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 break.h	787 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	759 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	944 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	546 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	4.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheops.h	3.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cdmm.h	3.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cevt-r4k.h	823 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	6.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clock.h	997 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 clocksource.h	884 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmp.h	492 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	5.28 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compat-signal.h	640 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat.h	6.66 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compiler.h	2.96 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cop2.h	1.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu-features.h	19.46 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpu-info.h	5.84 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpu-type.h	4.13 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpu.h	15.54 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpufeature.h	717 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 debug.h	654 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 dec	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 delay.h	841 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 device.h	347 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 div64.h	2.17 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 dma-coherence.h	813 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	981 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	9.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ds1287.h	1019 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dsemul.h	3.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dsp.h	1.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 edac.h	819 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	15.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 emma	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 errno.h	429 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 eva.h	796 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 exec.h	579 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable.h	241 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	372 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpregdef.h	2.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu.h	5.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu_emulator.h	5.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	2.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	4.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 fw	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 gio_device.h	1.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gt64120.h	19.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	544 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hazards.h	8.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	1.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hpet.h	1.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb.h	2.76 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hw_irq.h	475 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 i8259.h	2.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	330 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 idle.h	689 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 inst.h	2.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	18.44 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 ip32	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 irq.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_cpu.h	708 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_gt641xx.h	2.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_regs.h	744 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	4.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 isa-rev.h	556 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 isadep.h	603 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 jazz.h	8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jazzdma.h	2.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	1.4 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kdebug.h	303 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	1.53 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kgdb.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	221 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_host.h	37.88 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_para.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 lasat	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 linkage.h	306 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 llsc.h	623 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 local.h	4.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m48t37.h	732 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 maar.h	4.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 mach-ar7	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ath25	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ath79	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-au1x00	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-bcm47xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-bcm63xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-bmips	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-cavium-octeon	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-cobalt	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-db1x00	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-dec	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-emma2rh	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-generic	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ip22	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ip27	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ip28	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ip32	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-jazz	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-jz4740	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-lantiq	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-lasat	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-loongson32	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-loongson64	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-malta	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-netlogic	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-paravirt	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-pic32	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-pistachio	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-pmcs-msp71xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-pnx833x	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ralink	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-rc32434	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-rm	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-sibyte	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-tx39xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-tx49xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-vr41xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-xilfpga	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 machine.h	2.93 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mc146818-time.h	3.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc.h	450 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 mips-boards	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 mips-cm.h	15.86 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mips-cpc.h	5.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips-cps.h	6.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips-gic.h	12.3 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mips-r2-to-r6-emul.h	2.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips_machine.h	1.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips_mt.h	707 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mipsmtregs.h	10.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mipsprom.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mipsregs.h	88.1 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmu.h	550 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmu_context.h	5.41 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmzone.h	561 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 module.h	4.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msa.h	8.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msc01_ic.h	6.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 netlogic	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 nile4.h	10.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 octeon	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 paccess.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	7.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 pci	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 pci.h	4.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	482 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	3.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-32.h	7.31 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtable-64.h	10.87 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtable-bits.h	7.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	17.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm-cps.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm.h	3.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmon.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 prefetch.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	11.71 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 prom.h	845 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	5.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 r4k-timer.h	604 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 r4kcache.h	26.34 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 reboot.h	440 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 reg.h	26 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 regdef.h	2.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rtlx.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seccomp.h	800 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	607 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	884 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📁 sgi	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 sgialib.h	2.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sgiarcs.h	15.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	352 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 sibyte	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 sigcontext.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sim.h	2.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp-cps.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp-ops.h	2.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	3.31 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 sn	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 sni.h	7.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 socket.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sparsemem.h	486 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	459 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	188 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spram.h	262 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackframe.h	10.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackprotector.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	2.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	4.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	3.57 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 termios.h	2.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	6.63 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 time.h	2.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	2.87 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tlb.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbdebug.h	403 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbex.h	788 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	1.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbmisc.h	320 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	619 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	1.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 txx9	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 txx9irq.h	743 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 txx9pio.h	592 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 txx9tmr.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 types.h	487 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	22.2 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 uasm.h	9.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	1.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uprobes.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	3.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	1.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vpe.h	2.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 vr41xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 war.h	7.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 watch.h	827 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 wbflush.h	694 bytes	01/28/2018 09:20:33 PM	rw-r--r--
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Editing: nile4.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 *  asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions
 *
 *  Copyright (C) 2000 Geert Uytterhoeven <geert@linux-m68k.org>
 *		       Sony Software Development Center Europe (SDCE), Brussels
 *
 *  This file is based on the following documentation:
 *
 *	NEC Vrc 5074 System Controller Data Sheet, June 1998
 */

#ifndef _ASM_NILE4_H
#define _ASM_NILE4_H

#define NILE4_BASE		0xbfa00000
#define NILE4_SIZE		0x00200000		/* 2 MB */

/*
     *	Physical Device Address Registers (PDARs)
     */

#define NILE4_SDRAM0	0x0000	/* SDRAM Bank 0 [R/W] */
#define NILE4_SDRAM1	0x0008	/* SDRAM Bank 1 [R/W] */
#define NILE4_DCS2	0x0010	/* Device Chip-Select 2 [R/W] */
#define NILE4_DCS3	0x0018	/* Device Chip-Select 3 [R/W] */
#define NILE4_DCS4	0x0020	/* Device Chip-Select 4 [R/W] */
#define NILE4_DCS5	0x0028	/* Device Chip-Select 5 [R/W] */
#define NILE4_DCS6	0x0030	/* Device Chip-Select 6 [R/W] */
#define NILE4_DCS7	0x0038	/* Device Chip-Select 7 [R/W] */
#define NILE4_DCS8	0x0040	/* Device Chip-Select 8 [R/W] */
#define NILE4_PCIW0	0x0060	/* PCI Address Window 0 [R/W] */
#define NILE4_PCIW1	0x0068	/* PCI Address Window 1 [R/W] */
#define NILE4_INTCS	0x0070	/* Controller Internal Registers and Devices */
				/* [R/W] */
#define NILE4_BOOTCS	0x0078	/* Boot ROM Chip-Select [R/W] */

/*
     *	CPU Interface Registers
     */

#define NILE4_CPUSTAT	0x0080	/* CPU Status [R/W] */
#define NILE4_INTCTRL	0x0088	/* Interrupt Control [R/W] */
#define NILE4_INTSTAT0	0x0090	/* Interrupt Status 0 [R] */
#define NILE4_INTSTAT1	0x0098	/* Interrupt Status 1 and CPU Interrupt */
				/* Enable [R/W] */
#define NILE4_INTCLR	0x00A0	/* Interrupt Clear [R/W] */
#define NILE4_INTPPES	0x00A8	/* PCI Interrupt Control [R/W] */

/*
     *	Memory-Interface Registers
     */

#define NILE4_MEMCTRL	0x00C0	/* Memory Control */
#define NILE4_ACSTIME	0x00C8	/* Memory Access Timing [R/W] */
#define NILE4_CHKERR	0x00D0	/* Memory Check Error Status [R] */

/*
     *	PCI-Bus Registers
     */

#define NILE4_PCICTRL	0x00E0	/* PCI Control [R/W] */
#define NILE4_PCIARB	0x00E8	/* PCI Arbiter [R/W] */
#define NILE4_PCIINIT0	0x00F0	/* PCI Master (Initiator) 0 [R/W] */
#define NILE4_PCIINIT1	0x00F8	/* PCI Master (Initiator) 1 [R/W] */
#define NILE4_PCIERR	0x00B8	/* PCI Error [R/W] */

/*
     *	Local-Bus Registers
     */

#define NILE4_LCNFG	0x0100	/* Local Bus Configuration [R/W] */
#define NILE4_LCST2	0x0110	/* Local Bus Chip-Select Timing 2 [R/W] */
#define NILE4_LCST3	0x0118	/* Local Bus Chip-Select Timing 3 [R/W] */
#define NILE4_LCST4	0x0120	/* Local Bus Chip-Select Timing 4 [R/W] */
#define NILE4_LCST5	0x0128	/* Local Bus Chip-Select Timing 5 [R/W] */
#define NILE4_LCST6	0x0130	/* Local Bus Chip-Select Timing 6 [R/W] */
#define NILE4_LCST7	0x0138	/* Local Bus Chip-Select Timing 7 [R/W] */
#define NILE4_LCST8	0x0140	/* Local Bus Chip-Select Timing 8 [R/W] */
#define NILE4_DCSFN	0x0150	/* Device Chip-Select Muxing and Output */
				/* Enables [R/W] */
#define NILE4_DCSIO	0x0158	/* Device Chip-Selects As I/O Bits [R/W] */
#define NILE4_BCST	0x0178	/* Local Boot Chip-Select Timing [R/W] */

/*
     *	DMA Registers
     */

#define NILE4_DMACTRL0	0x0180	/* DMA Control 0 [R/W] */
#define NILE4_DMASRCA0	0x0188	/* DMA Source Address 0 [R/W] */
#define NILE4_DMADESA0	0x0190	/* DMA Destination Address 0 [R/W] */
#define NILE4_DMACTRL1	0x0198	/* DMA Control 1 [R/W] */
#define NILE4_DMASRCA1	0x01A0	/* DMA Source Address 1 [R/W] */
#define NILE4_DMADESA1	0x01A8	/* DMA Destination Address 1 [R/W] */

/*
     *	Timer Registers
     */

#define NILE4_T0CTRL	0x01C0	/* SDRAM Refresh Control [R/W] */
#define NILE4_T0CNTR	0x01C8	/* SDRAM Refresh Counter [R/W] */
#define NILE4_T1CTRL	0x01D0	/* CPU-Bus Read Time-Out Control [R/W] */
#define NILE4_T1CNTR	0x01D8	/* CPU-Bus Read Time-Out Counter [R/W] */
#define NILE4_T2CTRL	0x01E0	/* General-Purpose Timer Control [R/W] */
#define NILE4_T2CNTR	0x01E8	/* General-Purpose Timer Counter [R/W] */
#define NILE4_T3CTRL	0x01F0	/* Watchdog Timer Control [R/W] */
#define NILE4_T3CNTR	0x01F8	/* Watchdog Timer Counter [R/W] */

/*
     *	PCI Configuration Space Registers
     */

#define NILE4_PCI_BASE	0x0200

#define NILE4_VID	0x0200	/* PCI Vendor ID [R] */
#define NILE4_DID	0x0202	/* PCI Device ID [R] */
#define NILE4_PCICMD	0x0204	/* PCI Command [R/W] */
#define NILE4_PCISTS	0x0206	/* PCI Status [R/W] */
#define NILE4_REVID	0x0208	/* PCI Revision ID [R] */
#define NILE4_CLASS	0x0209	/* PCI Class Code [R] */
#define NILE4_CLSIZ	0x020C	/* PCI Cache Line Size [R/W] */
#define NILE4_MLTIM	0x020D	/* PCI Latency Timer [R/W] */
#define NILE4_HTYPE	0x020E	/* PCI Header Type [R] */
#define NILE4_BIST	0x020F	/* BIST [R] (unimplemented) */
#define NILE4_BARC	0x0210	/* PCI Base Address Register Control [R/W] */
#define NILE4_BAR0	0x0218	/* PCI Base Address Register 0 [R/W] */
#define NILE4_BAR1	0x0220	/* PCI Base Address Register 1 [R/W] */
#define NILE4_CIS	0x0228	/* PCI Cardbus CIS Pointer [R] */
				/* (unimplemented) */
#define NILE4_SSVID	0x022C	/* PCI Sub-System Vendor ID [R/W] */
#define NILE4_SSID	0x022E	/* PCI Sub-System ID [R/W] */
#define NILE4_ROM	0x0230	/* Expansion ROM Base Address [R] */
				/* (unimplemented) */
#define NILE4_INTLIN	0x023C	/* PCI Interrupt Line [R/W] */
#define NILE4_INTPIN	0x023D	/* PCI Interrupt Pin [R] */
#define NILE4_MINGNT	0x023E	/* PCI Min_Gnt [R] (unimplemented) */
#define NILE4_MAXLAT	0x023F	/* PCI Max_Lat [R] (unimplemented) */
#define NILE4_BAR2	0x0240	/* PCI Base Address Register 2 [R/W] */
#define NILE4_BAR3	0x0248	/* PCI Base Address Register 3 [R/W] */
#define NILE4_BAR4	0x0250	/* PCI Base Address Register 4 [R/W] */
#define NILE4_BAR5	0x0258	/* PCI Base Address Register 5 [R/W] */
#define NILE4_BAR6	0x0260	/* PCI Base Address Register 6 [R/W] */
#define NILE4_BAR7	0x0268	/* PCI Base Address Register 7 [R/W] */
#define NILE4_BAR8	0x0270	/* PCI Base Address Register 8 [R/W] */
#define NILE4_BARB	0x0278	/* PCI Base Address Register BOOT [R/W] */

/*
     *	Serial-Port Registers
     */

#define NILE4_UART_BASE 0x0300

#define NILE4_UARTRBR	0x0300	/* UART Receiver Data Buffer [R] */
#define NILE4_UARTTHR	0x0300	/* UART Transmitter Data Holding [W] */
#define NILE4_UARTIER	0x0308	/* UART Interrupt Enable [R/W] */
#define NILE4_UARTDLL	0x0300	/* UART Divisor Latch LSB [R/W] */
#define NILE4_UARTDLM	0x0308	/* UART Divisor Latch MSB [R/W] */
#define NILE4_UARTIIR	0x0310	/* UART Interrupt ID [R] */
#define NILE4_UARTFCR	0x0310	/* UART FIFO Control [W] */
#define NILE4_UARTLCR	0x0318	/* UART Line Control [R/W] */
#define NILE4_UARTMCR	0x0320	/* UART Modem Control [R/W] */
#define NILE4_UARTLSR	0x0328	/* UART Line Status [R/W] */
#define NILE4_UARTMSR	0x0330	/* UART Modem Status [R/W] */
#define NILE4_UARTSCR	0x0338	/* UART Scratch [R/W] */

#define NILE4_UART_BASE_BAUD	520833	/* 100 MHz / 12 / 16 */

/*
     *	Interrupt Lines
     */

#define NILE4_INT_CPCE	0	/* CPU-Interface Parity-Error Interrupt */
#define NILE4_INT_CNTD	1	/* CPU No-Target Decode Interrupt */
#define NILE4_INT_MCE	2	/* Memory-Check Error Interrupt */
#define NILE4_INT_DMA	3	/* DMA Controller Interrupt */
#define NILE4_INT_UART	4	/* UART Interrupt */
#define NILE4_INT_WDOG	5	/* Watchdog Timer Interrupt */
#define NILE4_INT_GPT	6	/* General-Purpose Timer Interrupt */
#define NILE4_INT_LBRTD 7	/* Local-Bus Ready Timer Interrupt */
#define NILE4_INT_INTA	8	/* PCI Interrupt Signal INTA# */
#define NILE4_INT_INTB	9	/* PCI Interrupt Signal INTB# */
#define NILE4_INT_INTC	10	/* PCI Interrupt Signal INTC# */
#define NILE4_INT_INTD	11	/* PCI Interrupt Signal INTD# */
#define NILE4_INT_INTE	12	/* PCI Interrupt Signal INTE# (ISA cascade) */
#define NILE4_INT_RESV	13	/* Reserved */
#define NILE4_INT_PCIS	14	/* PCI SERR# Interrupt */
#define NILE4_INT_PCIE	15	/* PCI Internal Error Interrupt */

/*
     *	Nile 4 Register Access
     */

static inline void nile4_sync(void)
{
    volatile u32 *p = (volatile u32 *)0xbfc00000;
    (void)(*p);
}

static inline void nile4_out32(u32 offset, u32 val)
{
    *(volatile u32 *)(NILE4_BASE+offset) = val;
    nile4_sync();
}

static inline u32 nile4_in32(u32 offset)
{
    u32 val = *(volatile u32 *)(NILE4_BASE+offset);
    nile4_sync();
    return val;
}

static inline void nile4_out16(u32 offset, u16 val)
{
    *(volatile u16 *)(NILE4_BASE+offset) = val;
    nile4_sync();
}

static inline u16 nile4_in16(u32 offset)
{
    u16 val = *(volatile u16 *)(NILE4_BASE+offset);
    nile4_sync();
    return val;
}

static inline void nile4_out8(u32 offset, u8 val)
{
    *(volatile u8 *)(NILE4_BASE+offset) = val;
    nile4_sync();
}

static inline u8 nile4_in8(u32 offset)
{
    u8 val = *(volatile u8 *)(NILE4_BASE+offset);
    nile4_sync();
    return val;
}

/*
     *	Physical Device Address Registers
     */

extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
			   int on_memory_bus, int visible);

/*
     *	PCI Master Registers
     */

#define NILE4_PCICMD_IACK	0	/* PCI Interrupt Acknowledge */
#define NILE4_PCICMD_IO		1	/* PCI I/O Space */
#define NILE4_PCICMD_MEM	3	/* PCI Memory Space */
#define NILE4_PCICMD_CFG	5	/* PCI Configuration Space */

/*
     *	PCI Address Spaces
     *
     *	Note that these are multiplexed using PCIINIT[01]!
     */

#define NILE4_PCI_IO_BASE	0xa6000000
#define NILE4_PCI_MEM_BASE	0xa8000000
#define NILE4_PCI_CFG_BASE	NILE4_PCI_MEM_BASE
#define NILE4_PCI_IACK_BASE	NILE4_PCI_IO_BASE

extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr);

/*
     *	Interrupt Programming
     */

#define NUM_I8259_INTERRUPTS	16
#define NUM_NILE4_INTERRUPTS	16

#define IRQ_I8259_CASCADE	NILE4_INT_INTE
#define is_i8259_irq(irq)	((irq) < NUM_I8259_INTERRUPTS)
#define nile4_to_irq(n)		((n)+NUM_I8259_INTERRUPTS)
#define irq_to_nile4(n)		((n)-NUM_I8259_INTERRUPTS)

extern void nile4_map_irq(int nile4_irq, int cpu_irq);
extern void nile4_map_irq_all(int cpu_irq);
extern void nile4_enable_irq(unsigned int nile4_irq);
extern void nile4_disable_irq(unsigned int nile4_irq);
extern void nile4_disable_irq_all(void);
extern u16 nile4_get_irq_stat(int cpu_irq);
extern void nile4_enable_irq_output(int cpu_irq);
extern void nile4_disable_irq_output(int cpu_irq);
extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
extern void nile4_clear_irq(int nile4_irq);
extern void nile4_clear_irq_mask(u32 mask);
extern u8 nile4_i8259_iack(void);
extern void nile4_dump_irq_status(void);	/* Debug */

#endif