OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:13 AM	rwxr-xr-x
📄 Kbuild	577 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 abi.h	853 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 addrspace.h	4.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amon.h	409 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 arch_hweight.h	792 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-eva.h	6.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	197 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm.h	8.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro-32.h	2.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro-64.h	1.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro.h	14.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	19.73 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 barrier.h	8.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcache.h	2.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	15.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitrev.h	608 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bmips-spaces.h	268 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bmips.h	3.45 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 bootinfo.h	5.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 branch.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 break.h	787 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	759 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	944 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	546 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	4.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheops.h	3.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cdmm.h	3.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cevt-r4k.h	823 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	6.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clock.h	997 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 clocksource.h	884 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmp.h	492 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	5.28 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compat-signal.h	640 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat.h	6.66 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compiler.h	2.96 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cop2.h	1.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu-features.h	19.46 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpu-info.h	5.84 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpu-type.h	4.13 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpu.h	15.54 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpufeature.h	717 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 debug.h	654 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 dec	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 delay.h	841 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 device.h	347 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 div64.h	2.17 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 dma-coherence.h	813 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	981 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	9.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ds1287.h	1019 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dsemul.h	3.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dsp.h	1.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 edac.h	819 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	15.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 emma	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 errno.h	429 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 eva.h	796 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 exec.h	579 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable.h	241 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	372 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpregdef.h	2.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu.h	5.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu_emulator.h	5.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	2.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	4.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 fw	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 gio_device.h	1.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gt64120.h	19.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	544 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hazards.h	8.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	1.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hpet.h	1.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb.h	2.76 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hw_irq.h	475 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 i8259.h	2.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	330 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 idle.h	689 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 inst.h	2.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	18.44 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 ip32	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 irq.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_cpu.h	708 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_gt641xx.h	2.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_regs.h	744 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	4.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 isa-rev.h	556 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 isadep.h	603 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 jazz.h	8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jazzdma.h	2.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	1.4 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kdebug.h	303 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	1.53 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kgdb.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	221 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_host.h	37.88 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_para.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 lasat	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 linkage.h	306 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 llsc.h	623 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 local.h	4.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m48t37.h	732 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 maar.h	4.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 mach-ar7	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ath25	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ath79	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-au1x00	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-bcm47xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-bcm63xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-bmips	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-cavium-octeon	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-cobalt	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-db1x00	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-dec	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-emma2rh	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-generic	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ip22	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ip27	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ip28	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ip32	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-jazz	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-jz4740	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-lantiq	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-lasat	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-loongson32	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-loongson64	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-malta	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-netlogic	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-paravirt	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-pic32	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-pistachio	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-pmcs-msp71xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-pnx833x	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-ralink	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-rc32434	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-rm	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-sibyte	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-tx39xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-tx49xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-vr41xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 mach-xilfpga	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 machine.h	2.93 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mc146818-time.h	3.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc.h	450 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 mips-boards	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 mips-cm.h	15.86 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mips-cpc.h	5.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips-cps.h	6.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips-gic.h	12.3 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mips-r2-to-r6-emul.h	2.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips_machine.h	1.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips_mt.h	707 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mipsmtregs.h	10.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mipsprom.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mipsregs.h	88.1 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmu.h	550 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmu_context.h	5.41 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmzone.h	561 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 module.h	4.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msa.h	8.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msc01_ic.h	6.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 netlogic	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 nile4.h	10.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 octeon	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 paccess.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	7.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 pci	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 pci.h	4.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	482 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	3.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-32.h	7.31 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtable-64.h	10.87 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtable-bits.h	7.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	17.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm-cps.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm.h	3.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmon.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 prefetch.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	11.71 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 prom.h	845 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	5.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 r4k-timer.h	604 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 r4kcache.h	26.34 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 reboot.h	440 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 reg.h	26 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 regdef.h	2.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rtlx.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seccomp.h	800 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	607 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	884 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📁 sgi	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 sgialib.h	2.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sgiarcs.h	15.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	352 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 sibyte	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 sigcontext.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sim.h	2.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp-cps.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp-ops.h	2.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	3.31 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 sn	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 sni.h	7.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 socket.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sparsemem.h	486 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	459 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	188 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spram.h	262 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackframe.h	10.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackprotector.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	2.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	4.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	3.57 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 termios.h	2.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	6.63 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 time.h	2.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	2.87 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tlb.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbdebug.h	403 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbex.h	788 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	1.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbmisc.h	320 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	619 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	1.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 txx9	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 txx9irq.h	743 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 txx9pio.h	592 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 txx9tmr.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 types.h	487 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	22.2 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 uasm.h	9.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	1.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uprobes.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	3.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	1.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vpe.h	2.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 vr41xx	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 war.h	7.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 watch.h	827 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 wbflush.h	694 bytes	01/28/2018 09:20:33 PM	rw-r--r--
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Editing: io.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 1995 Waldorf GmbH
 * Copyright (C) 1994 - 2000, 06 Ralf Baechle
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
 *	Author: Maciej W. Rozycki <macro@mips.com>
 */
#ifndef _ASM_IO_H
#define _ASM_IO_H

#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/irqflags.h>

#include <asm/addrspace.h>
#include <asm/bug.h>
#include <asm/byteorder.h>
#include <asm/cpu.h>
#include <asm/cpu-features.h>
#include <asm-generic/iomap.h>
#include <asm/page.h>
#include <asm/pgtable-bits.h>
#include <asm/processor.h>
#include <asm/string.h>

#include <ioremap.h>
#include <mangle-port.h>

/*
 * Slowdown I/O port space accesses for antique hardware.
 */
#undef CONF_SLOWDOWN_IO

/*
 * Raw operations are never swapped in software.  OTOH values that raw
 * operations are working on may or may not have been swapped by the bus
 * hardware.  An example use would be for flash memory that's used for
 * execute in place.
 */
# define __raw_ioswabb(a, x)	(x)
# define __raw_ioswabw(a, x)	(x)
# define __raw_ioswabl(a, x)	(x)
# define __raw_ioswabq(a, x)	(x)
# define ____raw_ioswabq(a, x)	(x)

/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */

#define IO_SPACE_LIMIT 0xffff

/*
 * On MIPS I/O ports are memory mapped, so we access them using normal
 * load/store instructions. mips_io_port_base is the virtual address to
 * which all ports are being mapped.  For sake of efficiency some code
 * assumes that this is an address that can be loaded with a single lui
 * instruction, so the lower 16 bits must be zero.  Should be true on
 * on any sane architecture; generic code does not use this assumption.
 */
extern unsigned long mips_io_port_base;

static inline void set_io_port_base(unsigned long base)
{
	mips_io_port_base = base;
}

/*
 * Thanks to James van Artsdalen for a better timing-fix than
 * the two short jumps: using outb's to a nonexistent port seems
 * to guarantee better timings even on fast machines.
 *
 * On the other hand, I'd like to be sure of a non-existent port:
 * I feel a bit unsafe about using 0x80 (should be safe, though)
 *
 *		Linus
 *
 */

#define __SLOW_DOWN_IO \
	__asm__ __volatile__( \
		"sb\t$0,0x80(%0)" \
		: : "r" (mips_io_port_base));

#ifdef CONF_SLOWDOWN_IO
#ifdef REALLY_SLOW_IO
#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
#else
#define SLOW_DOWN_IO __SLOW_DOWN_IO
#endif
#else
#define SLOW_DOWN_IO
#endif

/*
 *     virt_to_phys    -       map virtual addresses to physical
 *     @address: address to remap
 *
 *     The returned physical address is the physical (CPU) mapping for
 *     the memory address given. It is only valid to use this function on
 *     addresses directly mapped or allocated via kmalloc.
 *
 *     This function does not give bus mappings for DMA transfers. In
 *     almost all conceivable cases a device driver should not be using
 *     this function
 */
static inline unsigned long virt_to_phys(volatile const void *address)
{
	return __pa(address);
}

/*
 *     phys_to_virt    -       map physical address to virtual
 *     @address: address to remap
 *
 *     The returned virtual address is a current CPU mapping for
 *     the memory address given. It is only valid to use this function on
 *     addresses that have a kernel mapping
 *
 *     This function does not handle bus mappings for DMA transfers. In
 *     almost all conceivable cases a device driver should not be using
 *     this function
 */
static inline void * phys_to_virt(unsigned long address)
{
	return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
}

/*
 * ISA I/O bus memory addresses are 1:1 with the physical address.
 */
static inline unsigned long isa_virt_to_bus(volatile void *address)
{
	return virt_to_phys(address);
}

static inline void *isa_bus_to_virt(unsigned long address)
{
	return phys_to_virt(address);
}

#define isa_page_to_bus page_to_phys

/*
 * However PCI ones are not necessarily 1:1 and therefore these interfaces
 * are forbidden in portable PCI drivers.
 *
 * Allow them for x86 for legacy drivers, though.
 */
#define virt_to_bus virt_to_phys
#define bus_to_virt phys_to_virt

/*
 * Change "struct page" to physical address.
 */
#define page_to_phys(page)	((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)

extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);
extern void __iounmap(const volatile void __iomem *addr);

#ifndef CONFIG_PCI
struct pci_dev;
static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
#endif

static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,
	unsigned long flags)
{
	void __iomem *addr = plat_ioremap(offset, size, flags);

if (addr)
		return addr;

#define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL))

if (cpu_has_64bit_addresses) {
		u64 base = UNCAC_BASE;

/*
		 * R10000 supports a 2 bit uncached attribute therefore
		 * UNCAC_BASE may not equal IO_BASE.
		 */
		if (flags == _CACHE_UNCACHED)
			base = (u64) IO_BASE;
		return (void __iomem *) (unsigned long) (base + offset);
	} else if (__builtin_constant_p(offset) &&
		   __builtin_constant_p(size) && __builtin_constant_p(flags)) {
		phys_addr_t phys_addr, last_addr;

phys_addr = fixup_bigphys_addr(offset, size);

/* Don't allow wraparound or zero size. */
		last_addr = phys_addr + size - 1;
		if (!size || last_addr < phys_addr)
			return NULL;

/*
		 * Map uncached objects in the low 512MB of address
		 * space using KSEG1.
		 */
		if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
		    flags == _CACHE_UNCACHED)
			return (void __iomem *)
				(unsigned long)CKSEG1ADDR(phys_addr);
	}

return __ioremap(offset, size, flags);

#undef __IS_LOW512
}

/*
 * ioremap     -   map bus memory into CPU space
 * @offset:    bus address of the memory
 * @size:      size of the resource to map
 *
 * ioremap performs a platform specific sequence of operations to
 * make bus memory CPU accessible via the readb/readw/readl/writeb/
 * writew/writel functions and the other mmio helpers. The returned
 * address is not guaranteed to be usable directly as a virtual
 * address.
 */
#define ioremap(offset, size)						\
	__ioremap_mode((offset), (size), _CACHE_UNCACHED)

/*
 * ioremap_nocache     -   map bus memory into CPU space
 * @offset:    bus address of the memory
 * @size:      size of the resource to map
 *
 * ioremap_nocache performs a platform specific sequence of operations to
 * make bus memory CPU accessible via the readb/readw/readl/writeb/
 * writew/writel functions and the other mmio helpers. The returned
 * address is not guaranteed to be usable directly as a virtual
 * address.
 *
 * This version of ioremap ensures that the memory is marked uncachable
 * on the CPU as well as honouring existing caching rules from things like
 * the PCI bus. Note that there are other caches and buffers on many
 * busses. In particular driver authors should read up on PCI writes
 *
 * It's useful if some control registers are in such an area and
 * write combining or read caching is not desirable:
 */
#define ioremap_nocache(offset, size)					\
	__ioremap_mode((offset), (size), _CACHE_UNCACHED)
#define ioremap_uc ioremap_nocache

/*
 * ioremap_cachable -	map bus memory into CPU space
 * @offset:	    bus address of the memory
 * @size:	    size of the resource to map
 *
 * ioremap_nocache performs a platform specific sequence of operations to
 * make bus memory CPU accessible via the readb/readw/readl/writeb/
 * writew/writel functions and the other mmio helpers. The returned
 * address is not guaranteed to be usable directly as a virtual
 * address.
 *
 * This version of ioremap ensures that the memory is marked cachable by
 * the CPU.  Also enables full write-combining.	 Useful for some
 * memory-like regions on I/O busses.
 */
#define ioremap_cachable(offset, size)					\
	__ioremap_mode((offset), (size), _page_cachable_default)
#define ioremap_cache ioremap_cachable

/*
 * These two are MIPS specific ioremap variant.	 ioremap_cacheable_cow
 * requests a cachable mapping, ioremap_uncached_accelerated requests a
 * mapping using the uncached accelerated mode which isn't supported on
 * all processors.
 */
#define ioremap_cacheable_cow(offset, size)				\
	__ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
#define ioremap_uncached_accelerated(offset, size)			\
	__ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)

static inline void iounmap(const volatile void __iomem *addr)
{
	if (plat_iounmap(addr))
		return;

#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)

if (cpu_has_64bit_addresses ||
	    (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
		return;

__iounmap(addr);

#undef __IS_KSEG1
}

#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT)
#define war_io_reorder_wmb()		wmb()
#else
#define war_io_reorder_wmb()		barrier()
#endif

#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)			\
									\
static inline void pfx##write##bwlq(type val,				\
				    volatile void __iomem *mem)		\
{									\
	volatile type *__mem;						\
	type __val;							\
									\
	war_io_reorder_wmb();					\
									\
	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));	\
									\
	__val = pfx##ioswab##bwlq(__mem, val);				\
									\
	if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
		*__mem = __val;						\
	else if (cpu_has_64bits) {					\
		unsigned long __flags;					\
		type __tmp;						\
									\
		if (irq)						\
			local_irq_save(__flags);			\
		__asm__ __volatile__(					\
			".set	arch=r4000"	"\t\t# __writeq""\n\t"	\
			"dsll32 %L0, %L0, 0"			"\n\t"	\
			"dsrl32 %L0, %L0, 0"			"\n\t"	\
			"dsll32 %M0, %M0, 0"			"\n\t"	\
			"or	%L0, %L0, %M0"			"\n\t"	\
			"sd	%L0, %2"			"\n\t"	\
			".set	mips0"				"\n"	\
			: "=r" (__tmp)					\
			: "0" (__val), "m" (*__mem));			\
		if (irq)						\
			local_irq_restore(__flags);			\
	} else								\
		BUG();							\
}									\
									\
static inline type pfx##read##bwlq(const volatile void __iomem *mem)	\
{									\
	volatile type *__mem;						\
	type __val;							\
									\
	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));	\
									\
	if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
		__val = *__mem;						\
	else if (cpu_has_64bits) {					\
		unsigned long __flags;					\
									\
		if (irq)						\
			local_irq_save(__flags);			\
		__asm__ __volatile__(					\
			".set	arch=r4000"	"\t\t# __readq" "\n\t"	\
			"ld	%L0, %1"			"\n\t"	\
			"dsra32 %M0, %L0, 0"			"\n\t"	\
			"sll	%L0, %L0, 0"			"\n\t"	\
			".set	mips0"				"\n"	\
			: "=r" (__val)					\
			: "m" (*__mem));				\
		if (irq)						\
			local_irq_restore(__flags);			\
	} else {							\
		__val = 0;						\
		BUG();							\
	}								\
									\
	/* prevent prefetching of coherent DMA data prematurely */	\
	rmb();								\
	return pfx##ioswab##bwlq(__mem, __val);				\
}

#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)			\
									\
static inline void pfx##out##bwlq##p(type val, unsigned long port)	\
{									\
	volatile type *__addr;						\
	type __val;							\
									\
	war_io_reorder_wmb();					\
									\
	__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
									\
	__val = pfx##ioswab##bwlq(__addr, val);				\
									\
	/* Really, we want this to be atomic */				\
	BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));		\
									\
	*__addr = __val;						\
	slow;								\
}									\
									\
static inline type pfx##in##bwlq##p(unsigned long port)			\
{									\
	volatile type *__addr;						\
	type __val;							\
									\
	__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
									\
	BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));		\
									\
	__val = *__addr;						\
	slow;								\
									\
	/* prevent prefetching of coherent DMA data prematurely */	\
	rmb();								\
	return pfx##ioswab##bwlq(__addr, __val);			\
}

#define __BUILD_MEMORY_PFX(bus, bwlq, type)				\
									\
__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)

#define BUILDIO_MEM(bwlq, type)						\
									\
__BUILD_MEMORY_PFX(__raw_, bwlq, type)					\
__BUILD_MEMORY_PFX(, bwlq, type)					\
__BUILD_MEMORY_PFX(__mem_, bwlq, type)					\

BUILDIO_MEM(b, u8)
BUILDIO_MEM(w, u16)
BUILDIO_MEM(l, u32)
BUILDIO_MEM(q, u64)

#define __BUILD_IOPORT_PFX(bus, bwlq, type)				\
	__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)			\
	__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)

#define BUILDIO_IOPORT(bwlq, type)					\
	__BUILD_IOPORT_PFX(, bwlq, type)				\
	__BUILD_IOPORT_PFX(__mem_, bwlq, type)

BUILDIO_IOPORT(b, u8)
BUILDIO_IOPORT(w, u16)
BUILDIO_IOPORT(l, u32)
#ifdef CONFIG_64BIT
BUILDIO_IOPORT(q, u64)
#endif

#define __BUILDIO(bwlq, type)						\
									\
__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)

__BUILDIO(q, u64)

#define readb_relaxed			readb
#define readw_relaxed			readw
#define readl_relaxed			readl
#define readq_relaxed			readq

#define writeb_relaxed			writeb
#define writew_relaxed			writew
#define writel_relaxed			writel
#define writeq_relaxed			writeq

#define readb_be(addr)							\
	__raw_readb((__force unsigned *)(addr))
#define readw_be(addr)							\
	be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
#define readl_be(addr)							\
	be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
#define readq_be(addr)							\
	be64_to_cpu(__raw_readq((__force unsigned *)(addr)))

#define writeb_be(val, addr)						\
	__raw_writeb((val), (__force unsigned *)(addr))
#define writew_be(val, addr)						\
	__raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
#define writel_be(val, addr)						\
	__raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
#define writeq_be(val, addr)						\
	__raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))

/*
 * Some code tests for these symbols
 */
#define readq				readq
#define writeq				writeq

#define __BUILD_MEMORY_STRING(bwlq, type)				\
									\
static inline void writes##bwlq(volatile void __iomem *mem,		\
				const void *addr, unsigned int count)	\
{									\
	const volatile type *__addr = addr;				\
									\
	while (count--) {						\
		__mem_write##bwlq(*__addr, mem);			\
		__addr++;						\
	}								\
}									\
									\
static inline void reads##bwlq(volatile void __iomem *mem, void *addr,	\
			       unsigned int count)			\
{									\
	volatile type *__addr = addr;					\
									\
	while (count--) {						\
		*__addr = __mem_read##bwlq(mem);			\
		__addr++;						\
	}								\
}

#define __BUILD_IOPORT_STRING(bwlq, type)				\
									\
static inline void outs##bwlq(unsigned long port, const void *addr,	\
			      unsigned int count)			\
{									\
	const volatile type *__addr = addr;				\
									\
	while (count--) {						\
		__mem_out##bwlq(*__addr, port);				\
		__addr++;						\
	}								\
}									\
									\
static inline void ins##bwlq(unsigned long port, void *addr,		\
			     unsigned int count)			\
{									\
	volatile type *__addr = addr;					\
									\
	while (count--) {						\
		*__addr = __mem_in##bwlq(port);				\
		__addr++;						\
	}								\
}

#define BUILDSTRING(bwlq, type)						\
									\
__BUILD_MEMORY_STRING(bwlq, type)					\
__BUILD_IOPORT_STRING(bwlq, type)

BUILDSTRING(b, u8)
BUILDSTRING(w, u16)
BUILDSTRING(l, u32)
#ifdef CONFIG_64BIT
BUILDSTRING(q, u64)
#endif

#ifdef CONFIG_CPU_CAVIUM_OCTEON
#define mmiowb() wmb()
#else
/* Depends on MIPS II instruction set */
#define mmiowb() asm volatile ("sync" ::: "memory")
#endif

static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
{
	memset((void __force *) addr, val, count);
}
static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
{
	memcpy(dst, (void __force *) src, count);
}
static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
{
	memcpy((void __force *) dst, src, count);
}

/*
 * The caches on some architectures aren't dma-coherent and have need to
 * handle this in software.  There are three types of operations that
 * can be applied to dma buffers.
 *
 *  - dma_cache_wback_inv(start, size) makes caches and coherent by
 *    writing the content of the caches back to memory, if necessary.
 *    The function also invalidates the affected part of the caches as
 *    necessary before DMA transfers from outside to memory.
 *  - dma_cache_wback(start, size) makes caches and coherent by
 *    writing the content of the caches back to memory, if necessary.
 *    The function also invalidates the affected part of the caches as
 *    necessary before DMA transfers from outside to memory.
 *  - dma_cache_inv(start, size) invalidates the affected parts of the
 *    caches.  Dirty lines of the caches may be written back or simply
 *    be discarded.  This operation is necessary before dma operations
 *    to the memory.
 *
 * This API used to be exported; it now is for arch code internal use only.
 */
#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)

extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);

#define dma_cache_wback_inv(start, size)	_dma_cache_wback_inv(start, size)
#define dma_cache_wback(start, size)		_dma_cache_wback(start, size)
#define dma_cache_inv(start, size)		_dma_cache_inv(start, size)

#else /* Sane hardware */

#define dma_cache_wback_inv(start,size) \
	do { (void) (start); (void) (size); } while (0)
#define dma_cache_wback(start,size)	\
	do { (void) (start); (void) (size); } while (0)
#define dma_cache_inv(start,size)	\
	do { (void) (start); (void) (size); } while (0)

#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */

/*
 * Read a 32-bit register that requires a 64-bit read cycle on the bus.
 * Avoid interrupt mucking, just adjust the address for 4-byte access.
 * Assume the addresses are 8-byte aligned.
 */
#ifdef __MIPSEB__
#define __CSR_32_ADJUST 4
#else
#define __CSR_32_ADJUST 0
#endif

#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
#define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))

/*
 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 * access
 */
#define xlate_dev_mem_ptr(p)	__va(p)

/*
 * Convert a virtual cached pointer to an uncached pointer
 */
#define xlate_dev_kmem_ptr(p)	p

void __ioread64_copy(void *to, const void __iomem *from, size_t count);

#endif /* _ASM_IO_H */