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05/09/2024 07:14:12 AM
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Kbuild
599 bytes
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MC68328.h
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MC68EZ328.h
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MC68VZ328.h
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a.out-core.h
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adb_iop.h
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amigahw.h
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amipcmcia.h
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apollohw.h
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asm-offsets.h
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asm-prototypes.h
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atafd.h
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atafdreg.h
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atari_joystick.h
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atarikb.h
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atomic.h
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bitops.h
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blinken.h
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bootinfo.h
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bootstd.h
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bug.h
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bugs.h
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bvme6000hw.h
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cache.h
296 bytes
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cacheflush.h
133 bytes
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cacheflush_mm.h
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cacheflush_no.h
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checksum.h
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cmpxchg.h
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coldfire.h
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contregs.h
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current.h
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delay.h
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div64.h
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dma-mapping.h
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dma.h
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dsp56k.h
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dvma.h
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elf.h
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entry.h
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export.h
74 bytes
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fb.h
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fbio.h
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flat.h
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floppy.h
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fpu.h
535 bytes
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ftrace.h
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gpio.h
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hardirq.h
594 bytes
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hash.h
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hp300hw.h
186 bytes
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hwtest.h
467 bytes
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ide.h
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idprom.h
725 bytes
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intersil.h
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io.h
383 bytes
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io_mm.h
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io_no.h
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irq.h
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irqflags.h
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kexec.h
732 bytes
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linkage.h
1.55 KB
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m5206sim.h
6.4 KB
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m520xsim.h
7.15 KB
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m523xsim.h
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m525xsim.h
10.57 KB
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m5272sim.h
6.05 KB
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m527xsim.h
13.51 KB
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m528xsim.h
9.37 KB
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m52xxacr.h
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m5307sim.h
7.52 KB
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m53xxacr.h
3.6 KB
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m53xxsim.h
53.97 KB
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m5407sim.h
6.14 KB
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m5441xsim.h
8.5 KB
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m54xxacr.h
4.82 KB
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m54xxgpt.h
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m54xxpci.h
6.13 KB
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m54xxsim.h
3.8 KB
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mac_asc.h
520 bytes
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mac_baboon.h
999 bytes
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mac_iop.h
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mac_oss.h
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mac_psc.h
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mac_via.h
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machdep.h
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machines.h
3.13 KB
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machw.h
588 bytes
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macintosh.h
2.02 KB
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macints.h
3.28 KB
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math-emu.h
6.74 KB
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mc146818rtc.h
598 bytes
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mcf8390.h
3.75 KB
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mcf_pgalloc.h
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mcf_pgtable.h
9.89 KB
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mcfclk.h
1.01 KB
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mcfdma.h
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mcfgpio.h
8.48 KB
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mcfintc.h
3.09 KB
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mcfmmu.h
3.67 KB
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mcfpit.h
2.22 KB
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mcfqspi.h
1.82 KB
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mcfsim.h
1.5 KB
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mcfslt.h
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mcftimer.h
2.3 KB
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mcfuart.h
6.91 KB
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mcfwdebug.h
4.99 KB
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mmu.h
243 bytes
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mmu_context.h
7.2 KB
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mmzone.h
264 bytes
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module.h
847 bytes
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motorola_pgalloc.h
2.26 KB
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motorola_pgtable.h
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movs.h
1.44 KB
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mvme147hw.h
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mvme16xhw.h
2.16 KB
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natfeat.h
533 bytes
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nettel.h
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nubus.h
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openprom.h
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oplib.h
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page.h
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page_mm.h
4.06 KB
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page_no.h
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page_offset.h
256 bytes
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parport.h
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pci.h
458 bytes
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pgalloc.h
444 bytes
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pgtable.h
127 bytes
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pgtable_mm.h
4.84 KB
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pgtable_no.h
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processor.h
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ptrace.h
643 bytes
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q40_master.h
2.28 KB
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q40ints.h
749 bytes
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quicc_simple.h
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raw_io.h
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segment.h
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serial.h
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setup.h
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signal.h
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smp.h
32 bytes
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string.h
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sun3-head.h
353 bytes
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sun3_pgalloc.h
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sun3_pgtable.h
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sun3ints.h
989 bytes
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sun3mmu.h
4.91 KB
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sun3x.h
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sun3xflop.h
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sun3xprom.h
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switch_to.h
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thread_info.h
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timex.h
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tlb.h
486 bytes
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tlbflush.h
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traps.h
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uaccess.h
152 bytes
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uaccess_mm.h
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uaccess_no.h
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ucontext.h
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unaligned.h
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unistd.h
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user.h
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vga.h
651 bytes
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virtconvert.h
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zorro.h
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Editing: mcfmmu.h
Close
/* * mcfmmu.h -- definitions for the ColdFire v4e MMU * * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org> * * This file is subject to the terms and conditions of the GNU General Public * License. See the file COPYING in the main directory of this archive * for more details. */ #ifndef MCFMMU_H #define MCFMMU_H /* * The MMU support registers are mapped into the address space using * the processor MMUBASE register. We used a fixed address for mapping, * there doesn't seem any need to make this configurable yet. */ #define MMUBASE 0xfe000000 /* * The support registers of the MMU. Names are the sames as those * used in the Freescale v4e documentation. */ #define MMUCR (MMUBASE + 0x00) /* Control register */ #define MMUOR (MMUBASE + 0x04) /* Operation register */ #define MMUSR (MMUBASE + 0x08) /* Status register */ #define MMUAR (MMUBASE + 0x10) /* TLB Address register */ #define MMUTR (MMUBASE + 0x14) /* TLB Tag register */ #define MMUDR (MMUBASE + 0x18) /* TLB Data register */ /* * MMU Control register bit flags */ #define MMUCR_EN 0x00000001 /* Virtual mode enable */ #define MMUCR_ASM 0x00000002 /* Address space mode */ /* * MMU Operation register. */ #define MMUOR_UAA 0x00000001 /* Update allocation address */ #define MMUOR_ACC 0x00000002 /* TLB access */ #define MMUOR_RD 0x00000004 /* TLB access read */ #define MMUOR_WR 0x00000000 /* TLB access write */ #define MMUOR_ADR 0x00000008 /* TLB address select */ #define MMUOR_ITLB 0x00000010 /* ITLB operation */ #define MMUOR_CAS 0x00000020 /* Clear non-locked ASID TLBs */ #define MMUOR_CNL 0x00000040 /* Clear non-locked TLBs */ #define MMUOR_CA 0x00000080 /* Clear all TLBs */ #define MMUOR_STLB 0x00000100 /* Search TLBs */ #define MMUOR_AAN 16 /* TLB allocation address */ #define MMUOR_AAMASK 0xffff0000 /* AA mask */ /* * MMU Status register. */ #define MMUSR_HIT 0x00000002 /* Search TLB hit */ #define MMUSR_WF 0x00000008 /* Write access fault */ #define MMUSR_RF 0x00000010 /* Read access fault */ #define MMUSR_SPF 0x00000020 /* Supervisor protect fault */ /* * MMU Read/Write Tag register. */ #define MMUTR_V 0x00000001 /* Valid */ #define MMUTR_SG 0x00000002 /* Shared global */ #define MMUTR_IDN 2 /* Address Space ID */ #define MMUTR_IDMASK 0x000003fc /* ASID mask */ #define MMUTR_VAN 10 /* Virtual Address */ #define MMUTR_VAMASK 0xfffffc00 /* VA mask */ /* * MMU Read/Write Data register. */ #define MMUDR_LK 0x00000002 /* Lock entry */ #define MMUDR_X 0x00000004 /* Execute access enable */ #define MMUDR_W 0x00000008 /* Write access enable */ #define MMUDR_R 0x00000010 /* Read access enable */ #define MMUDR_SP 0x00000020 /* Supervisor access enable */ #define MMUDR_CM_CWT 0x00000000 /* Cachable write thru */ #define MMUDR_CM_CCB 0x00000040 /* Cachable copy back */ #define MMUDR_CM_NCP 0x00000080 /* Non-cachable precise */ #define MMUDR_CM_NCI 0x000000c0 /* Non-cachable imprecise */ #define MMUDR_SZ_1MB 0x00000000 /* 1MB page size */ #define MMUDR_SZ_4KB 0x00000100 /* 4kB page size */ #define MMUDR_SZ_8KB 0x00000200 /* 8kB page size */ #define MMUDR_SZ_1KB 0x00000300 /* 1kB page size */ #define MMUDR_PAN 10 /* Physical address */ #define MMUDR_PAMASK 0xfffffc00 /* PA mask */ #ifndef __ASSEMBLY__ /* * Simple access functions for the MMU registers. Nothing fancy * currently required, just simple 32bit access. */ static inline u32 mmu_read(u32 a) { return *((volatile u32 *) a); } static inline void mmu_write(u32 a, u32 v) { *((volatile u32 *) a) = v; __asm__ __volatile__ ("nop"); } void cf_bootmem_alloc(void); void cf_mmu_context_init(void); int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word); #endif #endif /* MCFMMU_H */