OXIESEC PANEL
- Current Dir:
/
/
usr
/
src
/
linux-headers-4.15.0-213
/
arch
/
m68k
/
include
/
asm
Server IP: 139.59.38.164
Upload:
Create Dir:
Name
Size
Modified
Perms
📁
..
-
05/09/2024 07:14:12 AM
rwxr-xr-x
📄
Kbuild
599 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
MC68328.h
37.82 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
MC68EZ328.h
37.74 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
MC68VZ328.h
41.02 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
a.out-core.h
1.98 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
adb_iop.h
1.09 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
amigahw.h
10.49 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
amigaints.h
3.5 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
amigayle.h
3.19 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
amipcmcia.h
2.51 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
apollohw.h
2.35 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
asm-offsets.h
35 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
asm-prototypes.h
211 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
atafd.h
300 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
atafdreg.h
2.68 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
atari_joystick.h
457 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
atari_stdma.h
514 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
atari_stram.h
528 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
atarihw.h
20.3 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
atariints.h
5.56 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
atarikb.h
1.4 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
atomic.h
4.86 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bitops.h
12.19 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
blinken.h
641 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
bootinfo.h
783 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
bootstd.h
4.64 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bug.h
659 bytes
06/16/2023 05:32:39 PM
rw-r--r--
📄
bugs.h
369 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
bvme6000hw.h
3.45 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cache.h
296 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
cacheflush.h
133 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
cacheflush_mm.h
6.92 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cacheflush_no.h
2.61 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
checksum.h
3.4 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cmpxchg.h
3.34 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
coldfire.h
1.61 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
contregs.h
3.31 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
current.h
580 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
delay.h
3.43 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
div64.h
858 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
dma-mapping.h
291 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
dma.h
16.65 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
dsp56k.h
1.24 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
dvma.h
9.67 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
elf.h
3.07 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
entry.h
5.76 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
export.h
74 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
fb.h
921 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
fbio.h
9.87 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
flat.h
1.02 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
floppy.h
5.06 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
fpu.h
535 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
ftrace.h
12 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
gpio.h
2.64 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
hardirq.h
594 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
hash.h
2.07 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
hp300hw.h
186 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
hwtest.h
467 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
ide.h
1.67 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
idprom.h
725 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
intersil.h
1.11 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
io.h
383 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
io_mm.h
16.19 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
io_no.h
5.26 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
irq.h
2.57 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
irqflags.h
1.61 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
kexec.h
732 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
linkage.h
1.55 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
m5206sim.h
6.4 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
m520xsim.h
7.15 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
m523xsim.h
7.7 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
m525xsim.h
10.57 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
m5272sim.h
6.05 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
m527xsim.h
13.51 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
m528xsim.h
9.37 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
m52xxacr.h
3.57 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
m5307sim.h
7.52 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
m53xxacr.h
3.6 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
m53xxsim.h
53.97 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
m5407sim.h
6.14 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
m5441xsim.h
8.5 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
m54xxacr.h
4.82 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
m54xxgpt.h
3.66 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
m54xxpci.h
6.13 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
m54xxsim.h
3.8 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mac_asc.h
520 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
mac_baboon.h
999 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
mac_iop.h
5.37 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mac_oss.h
1.83 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mac_psc.h
7.25 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mac_via.h
11.44 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
machdep.h
1.34 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
machines.h
3.13 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
machw.h
588 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
macintosh.h
2.02 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
macints.h
3.28 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
math-emu.h
6.74 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mc146818rtc.h
598 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
mcf8390.h
3.75 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mcf_pgalloc.h
2.37 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
mcf_pgtable.h
9.89 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mcfclk.h
1.01 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mcfdma.h
6.51 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mcfgpio.h
8.48 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mcfintc.h
3.09 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mcfmmu.h
3.67 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mcfpit.h
2.22 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mcfqspi.h
1.82 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mcfsim.h
1.5 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mcfslt.h
1.21 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mcftimer.h
2.3 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mcfuart.h
6.91 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mcfwdebug.h
4.99 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mmu.h
243 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
mmu_context.h
7.2 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mmzone.h
264 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
module.h
847 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
motorola_pgalloc.h
2.26 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
motorola_pgtable.h
9.2 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
movs.h
1.44 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mvme147hw.h
2.81 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mvme16xhw.h
2.16 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
natfeat.h
533 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
nettel.h
2.95 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
nubus.h
1.21 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
openprom.h
7.98 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
oplib.h
9.54 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
page.h
1.47 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
page_mm.h
4.06 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
page_no.h
1.28 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
page_offset.h
256 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
parport.h
837 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
pci.h
458 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
pgalloc.h
444 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
pgtable.h
127 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
pgtable_mm.h
4.84 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
pgtable_no.h
1.57 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
processor.h
3.59 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ptrace.h
643 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
q40_master.h
2.28 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
q40ints.h
749 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
quicc_simple.h
1.79 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
raw_io.h
11.41 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
segment.h
1.42 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
serial.h
1.14 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
setup.h
9.25 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
signal.h
1.34 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
smp.h
32 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
string.h
1.68 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
sun3-head.h
353 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
sun3_pgalloc.h
2.26 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
sun3_pgtable.h
7.65 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
sun3ints.h
989 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
sun3mmu.h
4.91 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
sun3x.h
868 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
sun3xflop.h
5.62 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
sun3xprom.h
1.31 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
switch_to.h
1.51 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
thread_info.h
2.02 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
timex.h
974 bytes
06/16/2023 05:32:39 PM
rw-r--r--
📄
tlb.h
486 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
tlbflush.h
5.95 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
traps.h
8.33 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
uaccess.h
152 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
uaccess_mm.h
10.31 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
uaccess_no.h
3.69 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ucontext.h
570 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
unaligned.h
600 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
unistd.h
952 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
user.h
3.78 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
vga.h
651 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
virtconvert.h
947 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
zorro.h
1.17 KB
01/28/2018 09:20:33 PM
rw-r--r--
Editing: m53xxacr.h
Close
/* SPDX-License-Identifier: GPL-2.0 */ /****************************************************************************/ /* * m53xxacr.h -- ColdFire version 3 core cache support * * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com> */ /****************************************************************************/ #ifndef m53xxacr_h #define m53xxacr_h /****************************************************************************/ /* * All varients of the ColdFire using version 3 cores have a similar * cache setup. They have a unified instruction and data cache, with * configurable write-through or copy-back operation. */ /* * Define the Cache Control register flags. */ #define CACR_EC 0x80000000 /* Enable cache */ #define CACR_ESB 0x20000000 /* Enable store buffer */ #define CACR_DPI 0x10000000 /* Disable invalidation by CPUSHL */ #define CACR_HLCK 0x08000000 /* Half cache lock mode */ #define CACR_CINVA 0x01000000 /* Invalidate cache */ #define CACR_DNFB 0x00000400 /* Inhibited fill buffer */ #define CACR_DCM_WT 0x00000000 /* Cacheable write-through */ #define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */ #define CACR_DCM_PRE 0x00000200 /* Cache inhibited, precise */ #define CACR_DCM_IMPRE 0x00000300 /* Cache inhibited, imprecise */ #define CACR_WPROTECT 0x00000020 /* Write protect*/ #define CACR_EUSP 0x00000010 /* Eanble separate user a7 */ /* * Define the Access Control register flags. */ #define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */ #define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */ #define ACR_ENABLE 0x00008000 /* Enable this ACR */ #define ACR_USER 0x00000000 /* Allow only user accesses */ #define ACR_SUPER 0x00002000 /* Allow supervisor access only */ #define ACR_ANY 0x00004000 /* Allow any access type */ #define ACR_CM_WT 0x00000000 /* Cacheable, write-through */ #define ACR_CM_CB 0x00000020 /* Cacheable, copy-back */ #define ACR_CM_PRE 0x00000040 /* Cache inhibited, precise */ #define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */ #define ACR_WPROTECT 0x00000004 /* Write protect region */ /* * Define the cache type and arrangement (needed for pushes). */ #if defined(CONFIG_M5307) #define CACHE_SIZE 0x2000 /* 8k of unified cache */ #define ICACHE_SIZE CACHE_SIZE #define DCACHE_SIZE CACHE_SIZE #elif defined(CONFIG_M53xx) #define CACHE_SIZE 0x4000 /* 16k of unified cache */ #define ICACHE_SIZE CACHE_SIZE #define DCACHE_SIZE CACHE_SIZE #endif #define CACHE_LINE_SIZE 16 /* 16 byte line size */ #define CACHE_WAYS 4 /* 4 ways - set associative */ /* * Set the cache controller settings we will use. This default in the * CACR is cache inhibited, we use the ACR register to set cacheing * enabled on the regions we want (eg RAM). */ #if defined(CONFIG_CACHE_COPYBACK) #define CACHE_TYPE ACR_CM_CB #define CACHE_PUSH #else #define CACHE_TYPE ACR_CM_WT #endif #ifdef CONFIG_COLDFIRE_SW_A7 #define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE) #else #define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP) #endif /* * Unified cache means we will never need to flush for coherency of * instruction fetch. We will need to flush to maintain memory/DMA * coherency though in all cases. And for copyback caches we will need * to push cached data as well. */ #define CACHE_INIT (CACHE_MODE + CACR_CINVA - CACR_EC) #define CACHE_INVALIDATE (CACHE_MODE + CACR_CINVA) #define CACHE_INVALIDATED (CACHE_MODE + CACR_CINVA) #define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ (0x000f0000) + \ (ACR_ENABLE + ACR_ANY + CACHE_TYPE)) #define ACR1_MODE 0 /****************************************************************************/ #endif /* m53xxsim_h */