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05/09/2024 07:14:12 AM
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Kbuild
599 bytes
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MC68328.h
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MC68EZ328.h
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MC68VZ328.h
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apollohw.h
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asm-offsets.h
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asm-prototypes.h
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atafd.h
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atafdreg.h
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bootinfo.h
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bootstd.h
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bugs.h
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bvme6000hw.h
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cache.h
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cacheflush.h
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cacheflush_mm.h
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cacheflush_no.h
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checksum.h
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cmpxchg.h
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coldfire.h
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contregs.h
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delay.h
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div64.h
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dma-mapping.h
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dma.h
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dsp56k.h
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dvma.h
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elf.h
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entry.h
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export.h
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fbio.h
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flat.h
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floppy.h
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fpu.h
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ftrace.h
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gpio.h
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hardirq.h
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hash.h
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hp300hw.h
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hwtest.h
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ide.h
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idprom.h
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intersil.h
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io.h
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io_mm.h
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io_no.h
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irq.h
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irqflags.h
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kexec.h
732 bytes
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linkage.h
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m5206sim.h
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m520xsim.h
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m523xsim.h
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m525xsim.h
10.57 KB
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m5272sim.h
6.05 KB
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m527xsim.h
13.51 KB
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m528xsim.h
9.37 KB
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m52xxacr.h
3.57 KB
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m5307sim.h
7.52 KB
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m53xxacr.h
3.6 KB
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m53xxsim.h
53.97 KB
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m5407sim.h
6.14 KB
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m5441xsim.h
8.5 KB
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m54xxacr.h
4.82 KB
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m54xxgpt.h
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m54xxpci.h
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m54xxsim.h
3.8 KB
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mac_asc.h
520 bytes
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mac_baboon.h
999 bytes
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mac_iop.h
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mac_oss.h
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mac_psc.h
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mac_via.h
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machdep.h
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machines.h
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machw.h
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macintosh.h
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macints.h
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math-emu.h
6.74 KB
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mc146818rtc.h
598 bytes
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mcf8390.h
3.75 KB
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mcf_pgalloc.h
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mcf_pgtable.h
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mcfclk.h
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mcfdma.h
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mcfgpio.h
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mcfintc.h
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mcfmmu.h
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mcfpit.h
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mcfqspi.h
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mcfsim.h
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mcfslt.h
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mcftimer.h
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mcfuart.h
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mcfwdebug.h
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mmu.h
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mmu_context.h
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mmzone.h
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module.h
847 bytes
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motorola_pgalloc.h
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motorola_pgtable.h
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movs.h
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mvme147hw.h
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mvme16xhw.h
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natfeat.h
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nettel.h
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nubus.h
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openprom.h
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oplib.h
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page.h
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page_mm.h
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page_no.h
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page_offset.h
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parport.h
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pci.h
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pgalloc.h
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pgtable.h
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pgtable_mm.h
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pgtable_no.h
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processor.h
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ptrace.h
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q40_master.h
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q40ints.h
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quicc_simple.h
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raw_io.h
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segment.h
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serial.h
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setup.h
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signal.h
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smp.h
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string.h
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sun3-head.h
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sun3_pgalloc.h
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sun3_pgtable.h
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sun3ints.h
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sun3mmu.h
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switch_to.h
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thread_info.h
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timex.h
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tlb.h
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tlbflush.h
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traps.h
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uaccess.h
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uaccess_mm.h
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uaccess_no.h
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ucontext.h
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unaligned.h
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unistd.h
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user.h
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vga.h
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virtconvert.h
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zorro.h
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Editing: m5407sim.h
Close
/* SPDX-License-Identifier: GPL-2.0 */ /****************************************************************************/ /* * m5407sim.h -- ColdFire 5407 System Integration Module support. * * (C) Copyright 2000, Lineo (www.lineo.com) * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd. * * Modified by David W. Miller for the MCF5307 Eval Board. */ /****************************************************************************/ #ifndef m5407sim_h #define m5407sim_h /****************************************************************************/ #define CPU_NAME "COLDFIRE(m5407)" #define CPU_INSTR_PER_JIFFY 3 #define MCF_BUSCLK (MCF_CLK / 2) #include <asm/m54xxacr.h> /* * Define the 5407 SIM register set addresses. */ #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/ #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */ #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */ #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */ #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */ #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */ #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ #define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */ #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */ #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */ #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */ #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */ #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */ #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */ #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */ #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */ #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */ #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */ #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */ #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */ #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */ #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */ #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */ #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */ #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */ #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */ #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */ #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */ #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */ #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */ #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ #define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */ #define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */ #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */ #define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */ #define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */ #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */ #define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */ #define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */ #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */ #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ #define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */ #define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */ #define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */ /* * Timer module. */ #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ #define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ #define MCFSIM_PADDR (MCF_MBAR + 0x244) #define MCFSIM_PADAT (MCF_MBAR + 0x248) /* * DMA unit base addresses. */ #define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ #define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ #define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ /* * Generic GPIO support */ #define MCFGPIO_PIN_MAX 16 #define MCFGPIO_IRQ_MAX -1 #define MCFGPIO_IRQ_VECBASE -1 /* * Some symbol defines for the above... */ #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */ #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ /* * Some symbol defines for the Parallel Port Pin Assignment Register */ #define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */ /* Clear to select par I/O */ #define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */ /* Clear to select par I/O */ /* * Defines for the IRQPAR Register */ #define IRQ5_LEVEL4 0x80 #define IRQ3_LEVEL6 0x40 #define IRQ1_LEVEL2 0x20 /* * Define system peripheral IRQ usage. */ #define MCF_IRQ_I2C0 29 /* I2C, Level 5 */ #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ #define MCF_IRQ_UART0 73 /* UART0 */ #define MCF_IRQ_UART1 74 /* UART1 */ /* * I2C module */ #define MCFI2C_BASE0 (MCF_MBAR + 0x280) #define MCFI2C_SIZE0 0x40 /****************************************************************************/ #endif /* m5407sim_h */