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05/09/2024 07:14:12 AM
rwxr-xr-x
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Kbuild
599 bytes
01/28/2018 09:20:33 PM
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MC68328.h
37.82 KB
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MC68EZ328.h
37.74 KB
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MC68VZ328.h
41.02 KB
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a.out-core.h
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adb_iop.h
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amigahw.h
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amigaints.h
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amigayle.h
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amipcmcia.h
2.51 KB
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apollohw.h
2.35 KB
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asm-offsets.h
35 bytes
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asm-prototypes.h
211 bytes
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atafd.h
300 bytes
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atafdreg.h
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atari_joystick.h
457 bytes
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atari_stdma.h
514 bytes
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atari_stram.h
528 bytes
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atarihw.h
20.3 KB
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atariints.h
5.56 KB
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atarikb.h
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atomic.h
4.86 KB
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bitops.h
12.19 KB
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blinken.h
641 bytes
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bootinfo.h
783 bytes
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bootstd.h
4.64 KB
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bug.h
659 bytes
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bugs.h
369 bytes
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bvme6000hw.h
3.45 KB
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cache.h
296 bytes
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cacheflush.h
133 bytes
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cacheflush_mm.h
6.92 KB
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cacheflush_no.h
2.61 KB
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checksum.h
3.4 KB
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cmpxchg.h
3.34 KB
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coldfire.h
1.61 KB
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contregs.h
3.31 KB
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current.h
580 bytes
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delay.h
3.43 KB
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div64.h
858 bytes
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dma-mapping.h
291 bytes
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dma.h
16.65 KB
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dsp56k.h
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dvma.h
9.67 KB
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elf.h
3.07 KB
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entry.h
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export.h
74 bytes
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fb.h
921 bytes
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fbio.h
9.87 KB
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flat.h
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floppy.h
5.06 KB
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fpu.h
535 bytes
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ftrace.h
12 bytes
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gpio.h
2.64 KB
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hardirq.h
594 bytes
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hash.h
2.07 KB
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hp300hw.h
186 bytes
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hwtest.h
467 bytes
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ide.h
1.67 KB
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idprom.h
725 bytes
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intersil.h
1.11 KB
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io.h
383 bytes
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io_mm.h
16.19 KB
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io_no.h
5.26 KB
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irq.h
2.57 KB
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irqflags.h
1.61 KB
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kexec.h
732 bytes
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linkage.h
1.55 KB
01/28/2018 09:20:33 PM
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m5206sim.h
6.4 KB
01/28/2018 09:20:33 PM
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m520xsim.h
7.15 KB
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m523xsim.h
7.7 KB
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m525xsim.h
10.57 KB
01/28/2018 09:20:33 PM
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m5272sim.h
6.05 KB
01/28/2018 09:20:33 PM
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m527xsim.h
13.51 KB
01/28/2018 09:20:33 PM
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m528xsim.h
9.37 KB
01/28/2018 09:20:33 PM
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m52xxacr.h
3.57 KB
01/28/2018 09:20:33 PM
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m5307sim.h
7.52 KB
01/28/2018 09:20:33 PM
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m53xxacr.h
3.6 KB
06/16/2023 05:32:39 PM
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m53xxsim.h
53.97 KB
01/28/2018 09:20:33 PM
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m5407sim.h
6.14 KB
01/28/2018 09:20:33 PM
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m5441xsim.h
8.5 KB
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m54xxacr.h
4.82 KB
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m54xxgpt.h
3.66 KB
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m54xxpci.h
6.13 KB
01/28/2018 09:20:33 PM
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m54xxsim.h
3.8 KB
01/28/2018 09:20:33 PM
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mac_asc.h
520 bytes
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mac_baboon.h
999 bytes
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mac_iop.h
5.37 KB
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mac_oss.h
1.83 KB
01/28/2018 09:20:33 PM
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mac_psc.h
7.25 KB
01/28/2018 09:20:33 PM
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mac_via.h
11.44 KB
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machdep.h
1.34 KB
01/28/2018 09:20:33 PM
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machines.h
3.13 KB
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machw.h
588 bytes
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macintosh.h
2.02 KB
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macints.h
3.28 KB
01/28/2018 09:20:33 PM
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math-emu.h
6.74 KB
01/28/2018 09:20:33 PM
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mc146818rtc.h
598 bytes
01/28/2018 09:20:33 PM
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mcf8390.h
3.75 KB
01/28/2018 09:20:33 PM
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mcf_pgalloc.h
2.37 KB
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mcf_pgtable.h
9.89 KB
01/28/2018 09:20:33 PM
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mcfclk.h
1.01 KB
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mcfdma.h
6.51 KB
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mcfgpio.h
8.48 KB
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mcfintc.h
3.09 KB
01/28/2018 09:20:33 PM
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mcfmmu.h
3.67 KB
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mcfpit.h
2.22 KB
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mcfqspi.h
1.82 KB
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mcfsim.h
1.5 KB
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mcfslt.h
1.21 KB
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mcftimer.h
2.3 KB
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mcfuart.h
6.91 KB
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mcfwdebug.h
4.99 KB
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mmu.h
243 bytes
01/28/2018 09:20:33 PM
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mmu_context.h
7.2 KB
01/28/2018 09:20:33 PM
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mmzone.h
264 bytes
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module.h
847 bytes
01/28/2018 09:20:33 PM
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motorola_pgalloc.h
2.26 KB
01/28/2018 09:20:33 PM
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motorola_pgtable.h
9.2 KB
01/28/2018 09:20:33 PM
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movs.h
1.44 KB
01/28/2018 09:20:33 PM
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mvme147hw.h
2.81 KB
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mvme16xhw.h
2.16 KB
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natfeat.h
533 bytes
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nettel.h
2.95 KB
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nubus.h
1.21 KB
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openprom.h
7.98 KB
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oplib.h
9.54 KB
01/28/2018 09:20:33 PM
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page.h
1.47 KB
01/28/2018 09:20:33 PM
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page_mm.h
4.06 KB
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page_no.h
1.28 KB
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page_offset.h
256 bytes
01/28/2018 09:20:33 PM
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parport.h
837 bytes
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pci.h
458 bytes
01/28/2018 09:20:33 PM
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pgalloc.h
444 bytes
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pgtable.h
127 bytes
01/28/2018 09:20:33 PM
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pgtable_mm.h
4.84 KB
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pgtable_no.h
1.57 KB
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processor.h
3.59 KB
01/28/2018 09:20:33 PM
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ptrace.h
643 bytes
01/28/2018 09:20:33 PM
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q40_master.h
2.28 KB
01/28/2018 09:20:33 PM
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q40ints.h
749 bytes
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quicc_simple.h
1.79 KB
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raw_io.h
11.41 KB
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segment.h
1.42 KB
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serial.h
1.14 KB
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setup.h
9.25 KB
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signal.h
1.34 KB
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smp.h
32 bytes
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string.h
1.68 KB
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sun3-head.h
353 bytes
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sun3_pgalloc.h
2.26 KB
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sun3_pgtable.h
7.65 KB
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sun3ints.h
989 bytes
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sun3mmu.h
4.91 KB
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sun3x.h
868 bytes
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sun3xflop.h
5.62 KB
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sun3xprom.h
1.31 KB
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switch_to.h
1.51 KB
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thread_info.h
2.02 KB
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timex.h
974 bytes
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tlb.h
486 bytes
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tlbflush.h
5.95 KB
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traps.h
8.33 KB
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uaccess.h
152 bytes
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uaccess_mm.h
10.31 KB
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uaccess_no.h
3.69 KB
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ucontext.h
570 bytes
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unaligned.h
600 bytes
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unistd.h
952 bytes
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user.h
3.78 KB
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vga.h
651 bytes
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virtconvert.h
947 bytes
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zorro.h
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Editing: cacheflush_mm.h
Close
/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _M68K_CACHEFLUSH_H #define _M68K_CACHEFLUSH_H #include <linux/mm.h> #ifdef CONFIG_COLDFIRE #include <asm/mcfsim.h> #endif /* cache code */ #define FLUSH_I_AND_D (0x00000808) #define FLUSH_I (0x00000008) #ifndef ICACHE_MAX_ADDR #define ICACHE_MAX_ADDR 0 #define ICACHE_SET_MASK 0 #define DCACHE_MAX_ADDR 0 #define DCACHE_SETMASK 0 #endif #ifndef CACHE_MODE #define CACHE_MODE 0 #define CACR_ICINVA 0 #define CACR_DCINVA 0 #define CACR_BCINVA 0 #endif /* * ColdFire architecture has no way to clear individual cache lines, so we * are stuck invalidating all the cache entries when we want a clear operation. */ static inline void clear_cf_icache(unsigned long start, unsigned long end) { __asm__ __volatile__ ( "movec %0,%%cacr\n\t" "nop" : : "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA)); } static inline void clear_cf_dcache(unsigned long start, unsigned long end) { __asm__ __volatile__ ( "movec %0,%%cacr\n\t" "nop" : : "r" (CACHE_MODE | CACR_DCINVA)); } static inline void clear_cf_bcache(unsigned long start, unsigned long end) { __asm__ __volatile__ ( "movec %0,%%cacr\n\t" "nop" : : "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA | CACR_DCINVA)); } /* * Use the ColdFire cpushl instruction to push (and invalidate) cache lines. * The start and end addresses are cache line numbers not memory addresses. */ static inline void flush_cf_icache(unsigned long start, unsigned long end) { unsigned long set; for (set = start; set <= end; set += (0x10 - 3)) { __asm__ __volatile__ ( "cpushl %%ic,(%0)\n\t" "addq%.l #1,%0\n\t" "cpushl %%ic,(%0)\n\t" "addq%.l #1,%0\n\t" "cpushl %%ic,(%0)\n\t" "addq%.l #1,%0\n\t" "cpushl %%ic,(%0)" : "=a" (set) : "a" (set)); } } static inline void flush_cf_dcache(unsigned long start, unsigned long end) { unsigned long set; for (set = start; set <= end; set += (0x10 - 3)) { __asm__ __volatile__ ( "cpushl %%dc,(%0)\n\t" "addq%.l #1,%0\n\t" "cpushl %%dc,(%0)\n\t" "addq%.l #1,%0\n\t" "cpushl %%dc,(%0)\n\t" "addq%.l #1,%0\n\t" "cpushl %%dc,(%0)" : "=a" (set) : "a" (set)); } } static inline void flush_cf_bcache(unsigned long start, unsigned long end) { unsigned long set; for (set = start; set <= end; set += (0x10 - 3)) { __asm__ __volatile__ ( "cpushl %%bc,(%0)\n\t" "addq%.l #1,%0\n\t" "cpushl %%bc,(%0)\n\t" "addq%.l #1,%0\n\t" "cpushl %%bc,(%0)\n\t" "addq%.l #1,%0\n\t" "cpushl %%bc,(%0)" : "=a" (set) : "a" (set)); } } /* * Cache handling functions */ static inline void flush_icache(void) { if (CPU_IS_COLDFIRE) { flush_cf_icache(0, ICACHE_MAX_ADDR); } else if (CPU_IS_040_OR_060) { asm volatile ( "nop\n" " .chip 68040\n" " cpusha %bc\n" " .chip 68k"); } else { unsigned long tmp; asm volatile ( "movec %%cacr,%0\n" " or.w %1,%0\n" " movec %0,%%cacr" : "=&d" (tmp) : "id" (FLUSH_I)); } } /* * invalidate the cache for the specified memory range. * It starts at the physical address specified for * the given number of bytes. */ extern void cache_clear(unsigned long paddr, int len); /* * push any dirty cache in the specified memory range. * It starts at the physical address specified for * the given number of bytes. */ extern void cache_push(unsigned long paddr, int len); /* * push and invalidate pages in the specified user virtual * memory range. */ extern void cache_push_v(unsigned long vaddr, int len); /* This is needed whenever the virtual mapping of the current process changes. */ #define __flush_cache_all() \ ({ \ if (CPU_IS_COLDFIRE) { \ flush_cf_dcache(0, DCACHE_MAX_ADDR); \ } else if (CPU_IS_040_OR_060) { \ __asm__ __volatile__("nop\n\t" \ ".chip 68040\n\t" \ "cpusha %dc\n\t" \ ".chip 68k"); \ } else { \ unsigned long _tmp; \ __asm__ __volatile__("movec %%cacr,%0\n\t" \ "orw %1,%0\n\t" \ "movec %0,%%cacr" \ : "=&d" (_tmp) \ : "di" (FLUSH_I_AND_D)); \ } \ }) #define __flush_cache_030() \ ({ \ if (CPU_IS_020_OR_030) { \ unsigned long _tmp; \ __asm__ __volatile__("movec %%cacr,%0\n\t" \ "orw %1,%0\n\t" \ "movec %0,%%cacr" \ : "=&d" (_tmp) \ : "di" (FLUSH_I_AND_D)); \ } \ }) #define flush_cache_all() __flush_cache_all() #define flush_cache_vmap(start, end) flush_cache_all() #define flush_cache_vunmap(start, end) flush_cache_all() static inline void flush_cache_mm(struct mm_struct *mm) { if (mm == current->mm) __flush_cache_030(); } #define flush_cache_dup_mm(mm) flush_cache_mm(mm) /* flush_cache_range/flush_cache_page must be macros to avoid a dependency on linux/mm.h, which includes this file... */ static inline void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { if (vma->vm_mm == current->mm) __flush_cache_030(); } static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn) { if (vma->vm_mm == current->mm) __flush_cache_030(); } /* Push the page at kernel virtual address and clear the icache */ /* RZ: use cpush %bc instead of cpush %dc, cinv %ic */ static inline void __flush_page_to_ram(void *vaddr) { if (CPU_IS_COLDFIRE) { unsigned long addr, start, end; addr = ((unsigned long) vaddr) & ~(PAGE_SIZE - 1); start = addr & ICACHE_SET_MASK; end = (addr + PAGE_SIZE - 1) & ICACHE_SET_MASK; if (start > end) { flush_cf_bcache(0, end); end = ICACHE_MAX_ADDR; } flush_cf_bcache(start, end); } else if (CPU_IS_040_OR_060) { __asm__ __volatile__("nop\n\t" ".chip 68040\n\t" "cpushp %%bc,(%0)\n\t" ".chip 68k" : : "a" (__pa(vaddr))); } else { unsigned long _tmp; __asm__ __volatile__("movec %%cacr,%0\n\t" "orw %1,%0\n\t" "movec %0,%%cacr" : "=&d" (_tmp) : "di" (FLUSH_I)); } } #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 #define flush_dcache_page(page) __flush_page_to_ram(page_address(page)) #define flush_dcache_mmap_lock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0) #define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page)) extern void flush_icache_user_range(struct vm_area_struct *vma, struct page *page, unsigned long addr, int len); extern void flush_icache_range(unsigned long address, unsigned long endaddr); static inline void copy_to_user_page(struct vm_area_struct *vma, struct page *page, unsigned long vaddr, void *dst, void *src, int len) { flush_cache_page(vma, vaddr, page_to_pfn(page)); memcpy(dst, src, len); flush_icache_user_range(vma, page, vaddr, len); } static inline void copy_from_user_page(struct vm_area_struct *vma, struct page *page, unsigned long vaddr, void *dst, void *src, int len) { flush_cache_page(vma, vaddr, page_to_pfn(page)); memcpy(dst, src, len); } #endif /* _M68K_CACHEFLUSH_H */