OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:12 AM	rwxr-xr-x
📄 Kbuild	599 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 MC68328.h	37.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 MC68EZ328.h	37.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 MC68VZ328.h	41.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 a.out-core.h	1.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 adb_iop.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amigahw.h	10.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amigaints.h	3.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amigayle.h	3.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amipcmcia.h	2.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 apollohw.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	211 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atafd.h	300 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atafdreg.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atari_joystick.h	457 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atari_stdma.h	514 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atari_stram.h	528 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atarihw.h	20.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atariints.h	5.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atarikb.h	1.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	4.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	12.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 blinken.h	641 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bootinfo.h	783 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bootstd.h	4.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	659 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 bugs.h	369 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bvme6000hw.h	3.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	296 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	133 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush_mm.h	6.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush_no.h	2.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	3.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 coldfire.h	1.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 contregs.h	3.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	580 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	3.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 div64.h	858 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	291 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	16.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dsp56k.h	1.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dvma.h	9.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 entry.h	5.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 export.h	74 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	921 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fbio.h	9.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flat.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	5.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu.h	535 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	12 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 gpio.h	2.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	594 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hash.h	2.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hp300hw.h	186 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hwtest.h	467 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	1.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 idprom.h	725 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 intersil.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	383 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io_mm.h	16.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io_no.h	5.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	2.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	1.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	732 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	1.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m5206sim.h	6.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m520xsim.h	7.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m523xsim.h	7.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m525xsim.h	10.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m5272sim.h	6.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m527xsim.h	13.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m528xsim.h	9.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m52xxacr.h	3.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m5307sim.h	7.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m53xxacr.h	3.6 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 m53xxsim.h	53.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m5407sim.h	6.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m5441xsim.h	8.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m54xxacr.h	4.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m54xxgpt.h	3.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m54xxpci.h	6.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m54xxsim.h	3.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_asc.h	520 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_baboon.h	999 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_iop.h	5.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_oss.h	1.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_psc.h	7.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_via.h	11.44 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 machdep.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 machines.h	3.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 machw.h	588 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 macintosh.h	2.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 macints.h	3.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 math-emu.h	6.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc.h	598 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcf8390.h	3.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcf_pgalloc.h	2.37 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mcf_pgtable.h	9.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfclk.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfdma.h	6.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfgpio.h	8.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfintc.h	3.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfmmu.h	3.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfpit.h	2.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfqspi.h	1.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfsim.h	1.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfslt.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcftimer.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfuart.h	6.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfwdebug.h	4.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	243 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	7.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone.h	264 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	847 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 motorola_pgalloc.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 motorola_pgtable.h	9.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 movs.h	1.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mvme147hw.h	2.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mvme16xhw.h	2.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 natfeat.h	533 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 nettel.h	2.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nubus.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 openprom.h	7.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 oplib.h	9.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	1.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_mm.h	4.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_no.h	1.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_offset.h	256 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 parport.h	837 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	458 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	444 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	127 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable_mm.h	4.84 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtable_no.h	1.57 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 processor.h	3.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	643 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 q40_master.h	2.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 q40ints.h	749 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 quicc_simple.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 raw_io.h	11.41 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 segment.h	1.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	1.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	9.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	32 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3-head.h	353 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3_pgalloc.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3_pgtable.h	7.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3ints.h	989 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3mmu.h	4.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3x.h	868 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3xflop.h	5.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3xprom.h	1.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	1.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	2.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	974 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 tlb.h	486 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	5.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	8.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	152 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess_mm.h	10.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess_no.h	3.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ucontext.h	570 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	600 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	952 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	3.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	651 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 virtconvert.h	947 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 zorro.h	1.17 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: dma.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _M68K_DMA_H
#define _M68K_DMA_H 1

#ifdef CONFIG_COLDFIRE
/*
 * ColdFire DMA Model:
 *   ColdFire DMA supports two forms of DMA: Single and Dual address. Single
 * address mode emits a source address, and expects that the device will either
 * pick up the data (DMA READ) or source data (DMA WRITE). This implies that
 * the device will place data on the correct byte(s) of the data bus, as the
 * memory transactions are always 32 bits. This implies that only 32 bit
 * devices will find single mode transfers useful. Dual address DMA mode
 * performs two cycles: source read and destination write. ColdFire will
 * align the data so that the device will always get the correct bytes, thus
 * is useful for 8 and 16 bit devices. This is the mode that is supported
 * below.
 *
 * AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000
 *               Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
 *
 * AUG/25/2000 : added support for 8, 16 and 32-bit Single-Address-Mode (K)2000
 *               Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
 *
 * APR/18/2002 : added proper support for MCF5272 DMA controller.
 *               Arthur Shipkowski (art@videon-central.com)
 */

#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfdma.h>

/*
 * Set number of channels of DMA on ColdFire for different implementations.
 */
#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
	defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
	defined(CONFIG_M528x) || defined(CONFIG_M525x)

#define MAX_M68K_DMA_CHANNELS 4
#elif defined(CONFIG_M5272)
#define MAX_M68K_DMA_CHANNELS 1
#elif defined(CONFIG_M53xx)
#define MAX_M68K_DMA_CHANNELS 0
#else
#define MAX_M68K_DMA_CHANNELS 2
#endif

extern unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS];
extern unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];

#if !defined(CONFIG_M5272)
#define DMA_MODE_WRITE_BIT  0x01  /* Memory/IO to IO/Memory select */
#define DMA_MODE_WORD_BIT   0x02  /* 8 or 16 bit transfers */
#define DMA_MODE_LONG_BIT   0x04  /* or 32 bit transfers */
#define DMA_MODE_SINGLE_BIT 0x08  /* single-address-mode */

/* I/O to memory, 8 bits, mode */
#define DMA_MODE_READ	            0
/* memory to I/O, 8 bits, mode */
#define DMA_MODE_WRITE	            1
/* I/O to memory, 16 bits, mode */
#define DMA_MODE_READ_WORD          2
/* memory to I/O, 16 bits, mode */
#define DMA_MODE_WRITE_WORD         3
/* I/O to memory, 32 bits, mode */
#define DMA_MODE_READ_LONG          4
/* memory to I/O, 32 bits, mode */
#define DMA_MODE_WRITE_LONG         5
/* I/O to memory, 8 bits, single-address-mode */
#define DMA_MODE_READ_SINGLE        8
/* memory to I/O, 8 bits, single-address-mode */
#define DMA_MODE_WRITE_SINGLE       9
/* I/O to memory, 16 bits, single-address-mode */
#define DMA_MODE_READ_WORD_SINGLE  10
/* memory to I/O, 16 bits, single-address-mode */
#define DMA_MODE_WRITE_WORD_SINGLE 11
/* I/O to memory, 32 bits, single-address-mode */
#define DMA_MODE_READ_LONG_SINGLE  12
/* memory to I/O, 32 bits, single-address-mode */
#define DMA_MODE_WRITE_LONG_SINGLE 13

#else /* CONFIG_M5272 is defined */

/* Source static-address mode */
#define DMA_MODE_SRC_SA_BIT 0x01
/* Two bits to select between all four modes */
#define DMA_MODE_SSIZE_MASK 0x06
/* Offset to shift bits in */
#define DMA_MODE_SSIZE_OFF  0x01
/* Destination static-address mode */
#define DMA_MODE_DES_SA_BIT 0x10
/* Two bits to select between all four modes */
#define DMA_MODE_DSIZE_MASK 0x60
/* Offset to shift bits in */
#define DMA_MODE_DSIZE_OFF  0x05
/* Size modifiers */
#define DMA_MODE_SIZE_LONG  0x00
#define DMA_MODE_SIZE_BYTE  0x01
#define DMA_MODE_SIZE_WORD  0x02
#define DMA_MODE_SIZE_LINE  0x03

/*
 * Aliases to help speed quick ports; these may be suboptimal, however. They
 * do not include the SINGLE mode modifiers since the MCF5272 does not have a
 * mode where the device is in control of its addressing.
 */

/* I/O to memory, 8 bits, mode */
#define DMA_MODE_READ	              ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
/* memory to I/O, 8 bits, mode */
#define DMA_MODE_WRITE	            ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
/* I/O to memory, 16 bits, mode */
#define DMA_MODE_READ_WORD	        ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
/* memory to I/O, 16 bits, mode */
#define DMA_MODE_WRITE_WORD         ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
/* I/O to memory, 32 bits, mode */
#define DMA_MODE_READ_LONG	        ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
/* memory to I/O, 32 bits, mode */
#define DMA_MODE_WRITE_LONG         ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)

#endif /* !defined(CONFIG_M5272) */

#if !defined(CONFIG_M5272)
/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
  volatile unsigned short *dmawp;

#ifdef DMA_DEBUG
  printk("enable_dma(dmanr=%d)\n", dmanr);
#endif

dmawp = (unsigned short *) dma_base_addr[dmanr];
  dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT;
}

static __inline__ void disable_dma(unsigned int dmanr)
{
  volatile unsigned short *dmawp;
  volatile unsigned char  *dmapb;

#ifdef DMA_DEBUG
  printk("disable_dma(dmanr=%d)\n", dmanr);
#endif

dmawp = (unsigned short *) dma_base_addr[dmanr];
  dmapb = (unsigned char *) dma_base_addr[dmanr];

/* Turn off external requests, and stop any DMA in progress */
  dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT;
  dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE;
}

/*
 * Clear the 'DMA Pointer Flip Flop'.
 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 * Use this once to initialize the FF to a known state.
 * After that, keep track of it. :-)
 * --- In order to do that, the DMA routines below should ---
 * --- only be used while interrupts are disabled! ---
 *
 * This is a NOP for ColdFire. Provide a stub for compatibility.
 */
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
}

/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{

volatile unsigned char  *dmabp;
  volatile unsigned short *dmawp;

#ifdef DMA_DEBUG
  printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
#endif

dmabp = (unsigned char *) dma_base_addr[dmanr];
  dmawp = (unsigned short *) dma_base_addr[dmanr];

/* Clear config errors */
  dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE;

/* Set command register */
  dmawp[MCFDMA_DCR] =
    MCFDMA_DCR_INT |         /* Enable completion irq */
    MCFDMA_DCR_CS |          /* Force one xfer per request */
    MCFDMA_DCR_AA |          /* Enable auto alignment */
    /* single-address-mode */
    ((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) |
    /* sets s_rw (-> r/w) high if Memory to I/0 */
    ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) |
    /* Memory to I/O or I/O to Memory */
    ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) |
    /* 32 bit, 16 bit or 8 bit transfers */
    ((mode & DMA_MODE_WORD_BIT)  ? MCFDMA_DCR_SSIZE_WORD :
     ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG :
                                   MCFDMA_DCR_SSIZE_BYTE)) |
    ((mode & DMA_MODE_WORD_BIT)  ? MCFDMA_DCR_DSIZE_WORD :
     ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_DSIZE_LONG :
                                   MCFDMA_DCR_DSIZE_BYTE));

#ifdef DEBUG_DMA
  printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__, __LINE__,
         dmanr, (int) &dmabp[MCFDMA_DSR], dmabp[MCFDMA_DSR],
	 (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR]);
#endif
}

/* Set transfer address for specific DMA channel */
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
{
  volatile unsigned short *dmawp;
  volatile unsigned int   *dmalp;

#ifdef DMA_DEBUG
  printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
#endif

dmawp = (unsigned short *) dma_base_addr[dmanr];
  dmalp = (unsigned int *) dma_base_addr[dmanr];

/* Determine which address registers are used for memory/device accesses */
  if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) {
    /* Source incrementing, must be memory */
    dmalp[MCFDMA_SAR] = a;
    /* Set dest address, must be device */
    dmalp[MCFDMA_DAR] = dma_device_address[dmanr];
  } else {
    /* Destination incrementing, must be memory */
    dmalp[MCFDMA_DAR] = a;
    /* Set source address, must be device */
    dmalp[MCFDMA_SAR] = dma_device_address[dmanr];
  }

#ifdef DEBUG_DMA
  printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
	__FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR],
	(int) &dmalp[MCFDMA_SAR], dmalp[MCFDMA_SAR],
	(int) &dmalp[MCFDMA_DAR], dmalp[MCFDMA_DAR]);
#endif
}

/*
 * Specific for Coldfire - sets device address.
 * Should be called after the mode set call, and before set DMA address.
 */
static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
{
#ifdef DMA_DEBUG
  printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
#endif

dma_device_address[dmanr] = a;
}

/*
 * NOTE 2: "count" represents _bytes_.
 */
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
  volatile unsigned short *dmawp;

#ifdef DMA_DEBUG
  printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
#endif

dmawp = (unsigned short *) dma_base_addr[dmanr];
  dmawp[MCFDMA_BCR] = (unsigned short)count;
}

/*
 * Get DMA residue count. After a DMA transfer, this
 * should return zero. Reading this while a DMA transfer is
 * still in progress will return unpredictable results.
 * Otherwise, it returns the number of _bytes_ left to transfer.
 */
static __inline__ int get_dma_residue(unsigned int dmanr)
{
  volatile unsigned short *dmawp;
  unsigned short count;

#ifdef DMA_DEBUG
  printk("get_dma_residue(dmanr=%d)\n", dmanr);
#endif

dmawp = (unsigned short *) dma_base_addr[dmanr];
  count = dmawp[MCFDMA_BCR];
  return((int) count);
}
#else /* CONFIG_M5272 is defined */

/*
 * The MCF5272 DMA controller is very different than the controller defined above
 * in terms of register mapping.  For instance, with the exception of the 16-bit
 * interrupt register (IRQ#85, for reference), all of the registers are 32-bit.
 *
 * The big difference, however, is the lack of device-requested DMA.  All modes
 * are dual address transfer, and there is no 'device' setup or direction bit.
 * You can DMA between a device and memory, between memory and memory, or even between
 * two devices directly, with any combination of incrementing and non-incrementing
 * addresses you choose.  This puts a crimp in distinguishing between the 'device
 * address' set up by set_dma_device_addr.
 *
 * Therefore, there are two options.  One is to use set_dma_addr and set_dma_device_addr,
 * which will act exactly as above in -- it will look to see if the source is set to
 * autoincrement, and if so it will make the source use the set_dma_addr value and the
 * destination the set_dma_device_addr value.  Otherwise the source will be set to the
 * set_dma_device_addr value and the destination will get the set_dma_addr value.
 *
 * The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions
 * and make it explicit.  Depending on what you're doing, one of these two should work
 * for you, but don't mix them in the same transfer setup.
 */

/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
  volatile unsigned int  *dmalp;

#ifdef DMA_DEBUG
  printk("enable_dma(dmanr=%d)\n", dmanr);
#endif

dmalp = (unsigned int *) dma_base_addr[dmanr];
  dmalp[MCFDMA_DMR] |= MCFDMA_DMR_EN;
}

static __inline__ void disable_dma(unsigned int dmanr)
{
  volatile unsigned int   *dmalp;

#ifdef DMA_DEBUG
  printk("disable_dma(dmanr=%d)\n", dmanr);
#endif

dmalp = (unsigned int *) dma_base_addr[dmanr];

/* Turn off external requests, and stop any DMA in progress */
  dmalp[MCFDMA_DMR] &= ~MCFDMA_DMR_EN;
  dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
}

/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{

volatile unsigned int   *dmalp;
  volatile unsigned short *dmawp;

#ifdef DMA_DEBUG
  printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
#endif
  dmalp = (unsigned int *) dma_base_addr[dmanr];
  dmawp = (unsigned short *) dma_base_addr[dmanr];

/* Clear config errors */
  dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;

/* Set command register */
  dmalp[MCFDMA_DMR] =
    MCFDMA_DMR_RQM_DUAL |         /* Mandatory Request Mode setting */
    MCFDMA_DMR_DSTT_SD  |         /* Set up addressing types; set to supervisor-data. */
    MCFDMA_DMR_SRCT_SD  |         /* Set up addressing types; set to supervisor-data. */
    /* source static-address-mode */
    ((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) |
    /* dest static-address-mode */
    ((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) |
    /* burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272 */
    (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) |
    (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF);

dmawp[MCFDMA_DIR] |= MCFDMA_DIR_ASCEN;   /* Enable completion interrupts */

#ifdef DEBUG_DMA
  printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__, __LINE__,
         dmanr, (int) &dmalp[MCFDMA_DMR], dmabp[MCFDMA_DMR],
	 (int) &dmawp[MCFDMA_DIR], dmawp[MCFDMA_DIR]);
#endif
}

/* Set transfer address for specific DMA channel */
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
{
  volatile unsigned int   *dmalp;

#ifdef DMA_DEBUG
  printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
#endif

dmalp = (unsigned int *) dma_base_addr[dmanr];

/* Determine which address registers are used for memory/device accesses */
  if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) {
    /* Source incrementing, must be memory */
    dmalp[MCFDMA_DSAR] = a;
    /* Set dest address, must be device */
    dmalp[MCFDMA_DDAR] = dma_device_address[dmanr];
  } else {
    /* Destination incrementing, must be memory */
    dmalp[MCFDMA_DDAR] = a;
    /* Set source address, must be device */
    dmalp[MCFDMA_DSAR] = dma_device_address[dmanr];
  }

#ifdef DEBUG_DMA
  printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
	__FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DMR], dmawp[MCFDMA_DMR],
	(int) &dmalp[MCFDMA_DSAR], dmalp[MCFDMA_DSAR],
	(int) &dmalp[MCFDMA_DDAR], dmalp[MCFDMA_DDAR]);
#endif
}

dma_device_address[dmanr] = a;
}

/*
 * NOTE 2: "count" represents _bytes_.
 *
 * NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value.
 */
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
  volatile unsigned int *dmalp;

#ifdef DMA_DEBUG
  printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
#endif

dmalp = (unsigned int *) dma_base_addr[dmanr];
  dmalp[MCFDMA_DBCR] = count;
}

#ifdef DMA_DEBUG
  printk("get_dma_residue(dmanr=%d)\n", dmanr);
#endif

dmalp = (unsigned int *) dma_base_addr[dmanr];
  count = dmalp[MCFDMA_DBCR];
  return(count);
}

#endif /* !defined(CONFIG_M5272) */
#endif /* CONFIG_COLDFIRE */

/* it's useless on the m68k, but unfortunately needed by the new
   bootmem allocator (but this should do it for this) */
#define MAX_DMA_ADDRESS PAGE_OFFSET

#define MAX_DMA_CHANNELS 8

extern int request_dma(unsigned int dmanr, const char * device_id);	/* reserve a DMA channel */
extern void free_dma(unsigned int dmanr);	/* release it again */

#ifdef CONFIG_PCI
extern int isa_dma_bridge_buggy;
#else
#define isa_dma_bridge_buggy    (0)
#endif

#endif /* _M68K_DMA_H */