OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:12 AM	rwxr-xr-x
📄 Kbuild	599 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 MC68328.h	37.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 MC68EZ328.h	37.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 MC68VZ328.h	41.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 a.out-core.h	1.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 adb_iop.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amigahw.h	10.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amigaints.h	3.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amigayle.h	3.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amipcmcia.h	2.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 apollohw.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	211 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atafd.h	300 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atafdreg.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atari_joystick.h	457 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atari_stdma.h	514 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atari_stram.h	528 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atarihw.h	20.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atariints.h	5.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atarikb.h	1.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	4.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	12.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 blinken.h	641 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bootinfo.h	783 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bootstd.h	4.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	659 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 bugs.h	369 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bvme6000hw.h	3.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	296 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	133 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush_mm.h	6.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush_no.h	2.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	3.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 coldfire.h	1.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 contregs.h	3.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	580 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	3.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 div64.h	858 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	291 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	16.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dsp56k.h	1.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dvma.h	9.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 entry.h	5.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 export.h	74 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	921 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fbio.h	9.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flat.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	5.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu.h	535 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	12 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 gpio.h	2.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	594 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hash.h	2.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hp300hw.h	186 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hwtest.h	467 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	1.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 idprom.h	725 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 intersil.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	383 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io_mm.h	16.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io_no.h	5.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	2.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	1.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	732 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	1.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m5206sim.h	6.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m520xsim.h	7.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m523xsim.h	7.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m525xsim.h	10.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m5272sim.h	6.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m527xsim.h	13.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m528xsim.h	9.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m52xxacr.h	3.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m5307sim.h	7.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m53xxacr.h	3.6 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 m53xxsim.h	53.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m5407sim.h	6.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m5441xsim.h	8.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m54xxacr.h	4.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m54xxgpt.h	3.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m54xxpci.h	6.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m54xxsim.h	3.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_asc.h	520 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_baboon.h	999 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_iop.h	5.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_oss.h	1.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_psc.h	7.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mac_via.h	11.44 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 machdep.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 machines.h	3.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 machw.h	588 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 macintosh.h	2.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 macints.h	3.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 math-emu.h	6.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc.h	598 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcf8390.h	3.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcf_pgalloc.h	2.37 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mcf_pgtable.h	9.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfclk.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfdma.h	6.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfgpio.h	8.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfintc.h	3.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfmmu.h	3.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfpit.h	2.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfqspi.h	1.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfsim.h	1.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfslt.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcftimer.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfuart.h	6.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcfwdebug.h	4.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	243 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	7.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone.h	264 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	847 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 motorola_pgalloc.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 motorola_pgtable.h	9.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 movs.h	1.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mvme147hw.h	2.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mvme16xhw.h	2.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 natfeat.h	533 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 nettel.h	2.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nubus.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 openprom.h	7.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 oplib.h	9.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	1.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_mm.h	4.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_no.h	1.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_offset.h	256 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 parport.h	837 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	458 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	444 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	127 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable_mm.h	4.84 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtable_no.h	1.57 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 processor.h	3.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	643 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 q40_master.h	2.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 q40ints.h	749 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 quicc_simple.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 raw_io.h	11.41 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 segment.h	1.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	1.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	9.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	32 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3-head.h	353 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3_pgalloc.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3_pgtable.h	7.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3ints.h	989 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3mmu.h	4.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3x.h	868 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3xflop.h	5.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun3xprom.h	1.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	1.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	2.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	974 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 tlb.h	486 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	5.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	8.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	152 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess_mm.h	10.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess_no.h	3.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ucontext.h	570 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	600 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	952 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	3.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	651 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 virtconvert.h	947 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 zorro.h	1.17 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: bitops.h

#ifndef _M68K_BITOPS_H
#define _M68K_BITOPS_H
/*
 * Copyright 1992, Linus Torvalds.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 */

#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif

#include <linux/compiler.h>
#include <asm/barrier.h>

/*
 *	Bit access functions vary across the ColdFire and 68k families.
 *	So we will break them out here, and then macro in the ones we want.
 *
 *	ColdFire - supports standard bset/bclr/bchg with register operand only
 *	68000    - supports standard bset/bclr/bchg with memory operand
 *	>= 68020 - also supports the bfset/bfclr/bfchg instructions
 *
 *	Although it is possible to use only the bset/bclr/bchg with register
 *	operands on all platforms you end up with larger generated code.
 *	So we use the best form possible on a given platform.
 */

static inline void bset_reg_set_bit(int nr, volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;

__asm__ __volatile__ ("bset %1,(%0)"
		:
		: "a" (p), "di" (nr & 7)
		: "memory");
}

static inline void bset_mem_set_bit(int nr, volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;

__asm__ __volatile__ ("bset %1,%0"
		: "+m" (*p)
		: "di" (nr & 7));
}

static inline void bfset_mem_set_bit(int nr, volatile unsigned long *vaddr)
{
	__asm__ __volatile__ ("bfset %1{%0:#1}"
		:
		: "d" (nr ^ 31), "o" (*vaddr)
		: "memory");
}

#if defined(CONFIG_COLDFIRE)
#define	set_bit(nr, vaddr)	bset_reg_set_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define	set_bit(nr, vaddr)	bset_mem_set_bit(nr, vaddr)
#else
#define set_bit(nr, vaddr)	(__builtin_constant_p(nr) ? \
				bset_mem_set_bit(nr, vaddr) : \
				bfset_mem_set_bit(nr, vaddr))
#endif

#define __set_bit(nr, vaddr)	set_bit(nr, vaddr)

static inline void bclr_reg_clear_bit(int nr, volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;

__asm__ __volatile__ ("bclr %1,(%0)"
		:
		: "a" (p), "di" (nr & 7)
		: "memory");
}

static inline void bclr_mem_clear_bit(int nr, volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;

__asm__ __volatile__ ("bclr %1,%0"
		: "+m" (*p)
		: "di" (nr & 7));
}

static inline void bfclr_mem_clear_bit(int nr, volatile unsigned long *vaddr)
{
	__asm__ __volatile__ ("bfclr %1{%0:#1}"
		:
		: "d" (nr ^ 31), "o" (*vaddr)
		: "memory");
}

#if defined(CONFIG_COLDFIRE)
#define	clear_bit(nr, vaddr)	bclr_reg_clear_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define	clear_bit(nr, vaddr)	bclr_mem_clear_bit(nr, vaddr)
#else
#define clear_bit(nr, vaddr)	(__builtin_constant_p(nr) ? \
				bclr_mem_clear_bit(nr, vaddr) : \
				bfclr_mem_clear_bit(nr, vaddr))
#endif

#define __clear_bit(nr, vaddr)	clear_bit(nr, vaddr)

static inline void bchg_reg_change_bit(int nr, volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;

__asm__ __volatile__ ("bchg %1,(%0)"
		:
		: "a" (p), "di" (nr & 7)
		: "memory");
}

static inline void bchg_mem_change_bit(int nr, volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;

__asm__ __volatile__ ("bchg %1,%0"
		: "+m" (*p)
		: "di" (nr & 7));
}

static inline void bfchg_mem_change_bit(int nr, volatile unsigned long *vaddr)
{
	__asm__ __volatile__ ("bfchg %1{%0:#1}"
		:
		: "d" (nr ^ 31), "o" (*vaddr)
		: "memory");
}

#if defined(CONFIG_COLDFIRE)
#define	change_bit(nr, vaddr)	bchg_reg_change_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define	change_bit(nr, vaddr)	bchg_mem_change_bit(nr, vaddr)
#else
#define change_bit(nr, vaddr)	(__builtin_constant_p(nr) ? \
				bchg_mem_change_bit(nr, vaddr) : \
				bfchg_mem_change_bit(nr, vaddr))
#endif

#define __change_bit(nr, vaddr)	change_bit(nr, vaddr)

static inline int test_bit(int nr, const volatile unsigned long *vaddr)
{
	return (vaddr[nr >> 5] & (1UL << (nr & 31))) != 0;
}

static inline int bset_reg_test_and_set_bit(int nr,
					    volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;
	char retval;

__asm__ __volatile__ ("bset %2,(%1); sne %0"
		: "=d" (retval)
		: "a" (p), "di" (nr & 7)
		: "memory");
	return retval;
}

static inline int bset_mem_test_and_set_bit(int nr,
					    volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;
	char retval;

__asm__ __volatile__ ("bset %2,%1; sne %0"
		: "=d" (retval), "+m" (*p)
		: "di" (nr & 7));
	return retval;
}

static inline int bfset_mem_test_and_set_bit(int nr,
					     volatile unsigned long *vaddr)
{
	char retval;

__asm__ __volatile__ ("bfset %2{%1:#1}; sne %0"
		: "=d" (retval)
		: "d" (nr ^ 31), "o" (*vaddr)
		: "memory");
	return retval;
}

#if defined(CONFIG_COLDFIRE)
#define	test_and_set_bit(nr, vaddr)	bset_reg_test_and_set_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define	test_and_set_bit(nr, vaddr)	bset_mem_test_and_set_bit(nr, vaddr)
#else
#define test_and_set_bit(nr, vaddr)	(__builtin_constant_p(nr) ? \
					bset_mem_test_and_set_bit(nr, vaddr) : \
					bfset_mem_test_and_set_bit(nr, vaddr))
#endif

#define __test_and_set_bit(nr, vaddr)	test_and_set_bit(nr, vaddr)

static inline int bclr_reg_test_and_clear_bit(int nr,
					      volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;
	char retval;

__asm__ __volatile__ ("bclr %2,(%1); sne %0"
		: "=d" (retval)
		: "a" (p), "di" (nr & 7)
		: "memory");
	return retval;
}

static inline int bclr_mem_test_and_clear_bit(int nr,
					      volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;
	char retval;

__asm__ __volatile__ ("bclr %2,%1; sne %0"
		: "=d" (retval), "+m" (*p)
		: "di" (nr & 7));
	return retval;
}

static inline int bfclr_mem_test_and_clear_bit(int nr,
					       volatile unsigned long *vaddr)
{
	char retval;

__asm__ __volatile__ ("bfclr %2{%1:#1}; sne %0"
		: "=d" (retval)
		: "d" (nr ^ 31), "o" (*vaddr)
		: "memory");
	return retval;
}

#if defined(CONFIG_COLDFIRE)
#define	test_and_clear_bit(nr, vaddr)	bclr_reg_test_and_clear_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define	test_and_clear_bit(nr, vaddr)	bclr_mem_test_and_clear_bit(nr, vaddr)
#else
#define test_and_clear_bit(nr, vaddr)	(__builtin_constant_p(nr) ? \
					bclr_mem_test_and_clear_bit(nr, vaddr) : \
					bfclr_mem_test_and_clear_bit(nr, vaddr))
#endif

#define __test_and_clear_bit(nr, vaddr)	test_and_clear_bit(nr, vaddr)

static inline int bchg_reg_test_and_change_bit(int nr,
					       volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;
	char retval;

__asm__ __volatile__ ("bchg %2,(%1); sne %0"
		: "=d" (retval)
		: "a" (p), "di" (nr & 7)
		: "memory");
	return retval;
}

static inline int bchg_mem_test_and_change_bit(int nr,
					       volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;
	char retval;

__asm__ __volatile__ ("bchg %2,%1; sne %0"
		: "=d" (retval), "+m" (*p)
		: "di" (nr & 7));
	return retval;
}

static inline int bfchg_mem_test_and_change_bit(int nr,
						volatile unsigned long *vaddr)
{
	char retval;

__asm__ __volatile__ ("bfchg %2{%1:#1}; sne %0"
		: "=d" (retval)
		: "d" (nr ^ 31), "o" (*vaddr)
		: "memory");
	return retval;
}

#if defined(CONFIG_COLDFIRE)
#define	test_and_change_bit(nr, vaddr)	bchg_reg_test_and_change_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define	test_and_change_bit(nr, vaddr)	bchg_mem_test_and_change_bit(nr, vaddr)
#else
#define test_and_change_bit(nr, vaddr)	(__builtin_constant_p(nr) ? \
					bchg_mem_test_and_change_bit(nr, vaddr) : \
					bfchg_mem_test_and_change_bit(nr, vaddr))
#endif

#define __test_and_change_bit(nr, vaddr) test_and_change_bit(nr, vaddr)

/*
 *	The true 68020 and more advanced processors support the "bfffo"
 *	instruction for finding bits. ColdFire and simple 68000 parts
 *	(including CPU32) do not support this. They simply use the generic
 *	functions.
 */
#if defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#include <asm-generic/bitops/find.h>
#include <asm-generic/bitops/ffz.h>
#else

static inline int find_first_zero_bit(const unsigned long *vaddr,
				      unsigned size)
{
	const unsigned long *p = vaddr;
	int res = 32;
	unsigned int words;
	unsigned long num;

if (!size)
		return 0;

words = (size + 31) >> 5;
	while (!(num = ~*p++)) {
		if (!--words)
			goto out;
	}

__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
			      : "=d" (res) : "d" (num & -num));
	res ^= 31;
out:
	res += ((long)p - (long)vaddr - 4) * 8;
	return res < size ? res : size;
}
#define find_first_zero_bit find_first_zero_bit

static inline int find_next_zero_bit(const unsigned long *vaddr, int size,
				     int offset)
{
	const unsigned long *p = vaddr + (offset >> 5);
	int bit = offset & 31UL, res;

if (offset >= size)
		return size;

if (bit) {
		unsigned long num = ~*p++ & (~0UL << bit);
		offset -= bit;

/* Look for zero in first longword */
		__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
				      : "=d" (res) : "d" (num & -num));
		if (res < 32) {
			offset += res ^ 31;
			return offset < size ? offset : size;
		}
		offset += 32;

if (offset >= size)
			return size;
	}
	/* No zero yet, search remaining full bytes for a zero */
	return offset + find_first_zero_bit(p, size - offset);
}
#define find_next_zero_bit find_next_zero_bit

static inline int find_first_bit(const unsigned long *vaddr, unsigned size)
{
	const unsigned long *p = vaddr;
	int res = 32;
	unsigned int words;
	unsigned long num;

if (!size)
		return 0;

words = (size + 31) >> 5;
	while (!(num = *p++)) {
		if (!--words)
			goto out;
	}

static inline int find_next_bit(const unsigned long *vaddr, int size,
				int offset)
{
	const unsigned long *p = vaddr + (offset >> 5);
	int bit = offset & 31UL, res;

if (offset >= size)
		return size;

if (bit) {
		unsigned long num = *p++ & (~0UL << bit);
		offset -= bit;

/* Look for one in first longword */
		__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
				      : "=d" (res) : "d" (num & -num));
		if (res < 32) {
			offset += res ^ 31;
			return offset < size ? offset : size;
		}
		offset += 32;

if (offset >= size)
			return size;
	}
	/* No one yet, search remaining full bytes for a one */
	return offset + find_first_bit(p, size - offset);
}
#define find_next_bit find_next_bit

/*
 * ffz = Find First Zero in word. Undefined if no zero exists,
 * so code should check against ~0UL first..
 */
static inline unsigned long ffz(unsigned long word)
{
	int res;

__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
			      : "=d" (res) : "d" (~word & -~word));
	return res ^ 31;
}

#endif

#ifdef __KERNEL__

#if defined(CONFIG_CPU_HAS_NO_BITFIELDS)

/*
 *	The newer ColdFire family members support a "bitrev" instruction
 *	and we can use that to implement a fast ffs. Older Coldfire parts,
 *	and normal 68000 parts don't have anything special, so we use the
 *	generic functions for those.
 */
#if (defined(__mcfisaaplus__) || defined(__mcfisac__)) && \
	!defined(CONFIG_M68000) && !defined(CONFIG_MCPU32)
static inline int __ffs(int x)
{
	__asm__ __volatile__ ("bitrev %0; ff1 %0"
		: "=d" (x)
		: "0" (x));
	return x;
}

static inline int ffs(int x)
{
	if (!x)
		return 0;
	return __ffs(x) + 1;
}

#else
#include <asm-generic/bitops/ffs.h>
#include <asm-generic/bitops/__ffs.h>
#endif

#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/__fls.h>

#else

/*
 *	ffs: find first bit set. This is defined the same way as
 *	the libc and compiler builtin ffs routines, therefore
 *	differs in spirit from the above ffz (man ffs).
 */
static inline int ffs(int x)
{
	int cnt;

__asm__ ("bfffo %1{#0:#0},%0"
		: "=d" (cnt)
		: "dm" (x & -x));
	return 32 - cnt;
}
#define __ffs(x) (ffs(x) - 1)

/*
 *	fls: find last bit set.
 */
static inline int fls(int x)
{
	int cnt;

__asm__ ("bfffo %1{#0,#0},%0"
		: "=d" (cnt)
		: "dm" (x));
	return 32 - cnt;
}

static inline int __fls(int x)
{
	return fls(x) - 1;
}

#endif

#include <asm-generic/bitops/ext2-atomic.h>
#include <asm-generic/bitops/le.h>
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>
#endif /* __KERNEL__ */

#endif /* _M68K_BITOPS_H */