OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 Kbuild	685 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-uaccess.h	4.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro.h	2.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	7.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	542 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	5.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bootparam.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	451 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	969 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheasm.h	3.77 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cacheflush.h	5.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 coprocessor.h	5.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	675 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	1.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	855 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	5.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flat.h	686 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	979 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.59 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 highmem.h	2.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_breakpoint.h	1.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	320 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 initialize_mmu.h	4.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmem_layout.h	2.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	462 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	3.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	525 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mxregs.h	1.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nommu_context.h	602 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	5.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-bridge.h	2.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	108 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	1.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	14.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 platform.h	1.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	7.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ptrace.h	3.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 regs.h	3.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 segment.h	376 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	443 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	561 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	502 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	967 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	4.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	412 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	1.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	2.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	601 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	982 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sysmem.h	426 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	3.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	1.79 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tlb.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	5.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	1.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 types.h	501 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	8.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ucontext.h	540 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	864 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	639 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	507 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vectors.h	4.05 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 vga.h	434 bytes	01/28/2018 09:20:33 PM	rw-r--r--

Name

Size

Modified

Perms

📁 ..

11/17/2022 06:42:16 AM

rwxr-xr-x

📄 Kbuild

685 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 asm-offsets.h

35 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 asm-uaccess.h

4.11 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 asmmacro.h

2.76 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 atomic.h

7.38 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 barrier.h

542 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 bitops.h

5.08 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bootparam.h

1.37 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bugs.h

451 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 cache.h

969 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 cacheasm.h

3.77 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 cacheflush.h

5.76 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 checksum.h

6 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cmpxchg.h

3.9 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 coprocessor.h

5.05 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 current.h

675 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 delay.h

1.63 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 dma-mapping.h

855 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 dma.h

1.79 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 elf.h

5.75 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 fixmap.h

2.5 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 flat.h

686 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 ftrace.h

979 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 futex.h

2.59 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 highmem.h

2.33 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 hw_breakpoint.h

1.45 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 hw_irq.h

320 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 initialize_mmu.h

4.58 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 io.h

2.09 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 irq.h

1.46 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 irqflags.h

1.99 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 kmem_layout.h

2.07 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu.h

462 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu_context.h

3.62 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 module.h

525 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 mxregs.h

1.3 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 nommu_context.h

602 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 page.h

5.69 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pci-bridge.h

2.16 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pci.h

1.37 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 perf_event.h

108 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgalloc.h

1.84 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgtable.h

14.89 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 platform.h

1.75 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 processor.h

7.44 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 ptrace.h

3.74 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 regs.h

3.87 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 segment.h

376 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 serial.h

443 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 shmparam.h

561 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 signal.h

502 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 smp.h

967 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 spinlock.h

4.6 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 spinlock_types.h

412 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 stacktrace.h

1.13 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 string.h

2.65 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 switch_to.h

601 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 syscall.h

982 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 sysmem.h

426 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 thread_info.h

3.62 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 timex.h

1.79 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 tlb.h

1.1 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 tlbflush.h

5.53 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 traps.h

1.87 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 types.h

501 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 uaccess.h

8.67 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 ucontext.h

540 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 unaligned.h

864 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 unistd.h

639 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 user.h

507 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 vectors.h

4.05 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 vga.h

434 bytes

01/28/2018 09:20:33 PM

rw-r--r--

Editing: string.h

/*
 * include/asm-xtensa/string.h
 *
 * These trivial string functions are considered part of the public domain.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2001 - 2005 Tensilica Inc.
 */

/* We should optimize these. See arch/xtensa/lib/strncpy_user.S */

#ifndef _XTENSA_STRING_H
#define _XTENSA_STRING_H

#define __HAVE_ARCH_STRCPY
static inline char *strcpy(char *__dest, const char *__src)
{
	register char *__xdest = __dest;
	unsigned long __dummy;

__asm__ __volatile__("1:\n\t"
		"l8ui	%2, %1, 0\n\t"
		"s8i	%2, %0, 0\n\t"
		"addi	%1, %1, 1\n\t"
		"addi	%0, %0, 1\n\t"
		"bnez	%2, 1b\n\t"
		: "=r" (__dest), "=r" (__src), "=&r" (__dummy)
		: "0" (__dest), "1" (__src)
		: "memory");

return __xdest;
}

#define __HAVE_ARCH_STRNCPY
static inline char *strncpy(char *__dest, const char *__src, size_t __n)
{
	register char *__xdest = __dest;
	unsigned long __dummy;

if (__n == 0)
		return __xdest;

__asm__ __volatile__(
		"1:\n\t"
		"l8ui	%2, %1, 0\n\t"
		"s8i	%2, %0, 0\n\t"
		"addi	%1, %1, 1\n\t"
		"addi	%0, %0, 1\n\t"
		"beqz	%2, 2f\n\t"
		"bne	%1, %5, 1b\n"
		"2:"
		: "=r" (__dest), "=r" (__src), "=&r" (__dummy)
		: "0" (__dest), "1" (__src), "r" (__src+__n)
		: "memory");

return __xdest;
}

#define __HAVE_ARCH_STRCMP
static inline int strcmp(const char *__cs, const char *__ct)
{
	register int __res;
	unsigned long __dummy;

__asm__ __volatile__(
		"1:\n\t"
		"l8ui	%3, %1, 0\n\t"
		"addi	%1, %1, 1\n\t"
		"l8ui	%2, %0, 0\n\t"
		"addi	%0, %0, 1\n\t"
		"beqz	%2, 2f\n\t"
		"beq	%2, %3, 1b\n"
		"2:\n\t"
		"sub	%2, %2, %3"
		: "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&r" (__dummy)
		: "0" (__cs), "1" (__ct));

return __res;
}

#define __HAVE_ARCH_STRNCMP
static inline int strncmp(const char *__cs, const char *__ct, size_t __n)
{
	register int __res;
	unsigned long __dummy;

__asm__ __volatile__(
		"mov	%2, %3\n"
		"1:\n\t"
		"beq	%0, %6, 2f\n\t"
		"l8ui	%3, %1, 0\n\t"
		"addi	%1, %1, 1\n\t"
		"l8ui	%2, %0, 0\n\t"
		"addi	%0, %0, 1\n\t"
		"beqz	%2, 2f\n\t"
		"beqz	%3, 2f\n\t"
		"beq	%2, %3, 1b\n"
		"2:\n\t"
		"sub	%2, %2, %3"
		: "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&r" (__dummy)
		: "0" (__cs), "1" (__ct), "r" (__cs+__n));

return __res;
}

#define __HAVE_ARCH_MEMSET
extern void *memset(void *__s, int __c, size_t __count);

#define __HAVE_ARCH_MEMCPY
extern void *memcpy(void *__to, __const__ void *__from, size_t __n);

#define __HAVE_ARCH_MEMMOVE
extern void *memmove(void *__dest, __const__ void *__src, size_t __n);

/* Don't build bcopy at all ...  */
#define __HAVE_ARCH_BCOPY

#endif	/* _XTENSA_STRING_H */