OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 Kbuild	685 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-uaccess.h	4.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro.h	2.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	7.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	542 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	5.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bootparam.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	451 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	969 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheasm.h	3.77 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cacheflush.h	5.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 coprocessor.h	5.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	675 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	1.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	855 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	5.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flat.h	686 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	979 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.59 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 highmem.h	2.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_breakpoint.h	1.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	320 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 initialize_mmu.h	4.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmem_layout.h	2.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	462 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	3.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	525 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mxregs.h	1.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nommu_context.h	602 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	5.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-bridge.h	2.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	108 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	1.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	14.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 platform.h	1.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	7.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ptrace.h	3.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 regs.h	3.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 segment.h	376 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	443 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	561 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	502 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	967 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	4.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	412 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	1.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	2.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	601 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	982 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sysmem.h	426 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	3.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	1.79 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tlb.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	5.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	1.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 types.h	501 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	8.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ucontext.h	540 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	864 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	639 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	507 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vectors.h	4.05 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 vga.h	434 bytes	01/28/2018 09:20:33 PM	rw-r--r--

Name

Size

Modified

Perms

📁 ..

11/17/2022 06:42:16 AM

rwxr-xr-x

📄 Kbuild

685 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 asm-offsets.h

35 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 asm-uaccess.h

4.11 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 asmmacro.h

2.76 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 atomic.h

7.38 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 barrier.h

542 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 bitops.h

5.08 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bootparam.h

1.37 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bugs.h

451 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 cache.h

969 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 cacheasm.h

3.77 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 cacheflush.h

5.76 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 checksum.h

6 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cmpxchg.h

3.9 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 coprocessor.h

5.05 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 current.h

675 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 delay.h

1.63 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 dma-mapping.h

855 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 dma.h

1.79 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 elf.h

5.75 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 fixmap.h

2.5 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 flat.h

686 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 ftrace.h

979 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 futex.h

2.59 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 highmem.h

2.33 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 hw_breakpoint.h

1.45 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 hw_irq.h

320 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 initialize_mmu.h

4.58 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 io.h

2.09 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 irq.h

1.46 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 irqflags.h

1.99 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 kmem_layout.h

2.07 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu.h

462 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu_context.h

3.62 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 module.h

525 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 mxregs.h

1.3 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 nommu_context.h

602 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 page.h

5.69 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pci-bridge.h

2.16 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pci.h

1.37 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 perf_event.h

108 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgalloc.h

1.84 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgtable.h

14.89 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 platform.h

1.75 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 processor.h

7.44 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 ptrace.h

3.74 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 regs.h

3.87 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 segment.h

376 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 serial.h

443 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 shmparam.h

561 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 signal.h

502 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 smp.h

967 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 spinlock.h

4.6 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 spinlock_types.h

412 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 stacktrace.h

1.13 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 string.h

2.65 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 switch_to.h

601 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 syscall.h

982 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 sysmem.h

426 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 thread_info.h

3.62 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 timex.h

1.79 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 tlb.h

1.1 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 tlbflush.h

5.53 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 traps.h

1.87 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 types.h

501 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 uaccess.h

8.67 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 ucontext.h

540 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 unaligned.h

864 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 unistd.h

639 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 user.h

507 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 vectors.h

4.05 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 vga.h

434 bytes

01/28/2018 09:20:33 PM

rw-r--r--

Editing: mmu_context.h

/*
 * Switch an MMU context.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2001 - 2013 Tensilica Inc.
 */

#ifndef _XTENSA_MMU_CONTEXT_H
#define _XTENSA_MMU_CONTEXT_H

#ifndef CONFIG_MMU
#include <asm/nommu_context.h>
#else

#include <linux/stringify.h>
#include <linux/sched.h>
#include <linux/mm_types.h>

#include <asm/vectors.h>

#include <asm/pgtable.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm-generic/mm_hooks.h>
#include <asm-generic/percpu.h>

#if (XCHAL_HAVE_TLBS != 1)
# error "Linux must have an MMU!"
#endif

DECLARE_PER_CPU(unsigned long, asid_cache);
#define cpu_asid_cache(cpu) per_cpu(asid_cache, cpu)

/*
 * NO_CONTEXT is the invalid ASID value that we don't ever assign to
 * any user or kernel context.  We use the reserved values in the
 * ASID_INSERT macro below.
 *
 * 0 invalid
 * 1 kernel
 * 2 reserved
 * 3 reserved
 * 4...255 available
 */

#define NO_CONTEXT	0
#define ASID_USER_FIRST	4
#define ASID_MASK	((1 << XCHAL_MMU_ASID_BITS) - 1)
#define ASID_INSERT(x)	(0x03020001 | (((x) & ASID_MASK) << 8))

void init_mmu(void);

static inline void set_rasid_register (unsigned long val)
{
	__asm__ __volatile__ (" wsr %0, rasid\n\t"
			      " isync\n" : : "a" (val));
}

static inline unsigned long get_rasid_register (void)
{
	unsigned long tmp;
	__asm__ __volatile__ (" rsr %0, rasid\n\t" : "=a" (tmp));
	return tmp;
}

static inline void get_new_mmu_context(struct mm_struct *mm, unsigned int cpu)
{
	unsigned long asid = cpu_asid_cache(cpu);
	if ((++asid & ASID_MASK) == 0) {
		/*
		 * Start new asid cycle; continue counting with next
		 * incarnation bits; skipping over 0, 1, 2, 3.
		 */
		local_flush_tlb_all();
		asid += ASID_USER_FIRST;
	}
	cpu_asid_cache(cpu) = asid;
	mm->context.asid[cpu] = asid;
	mm->context.cpu = cpu;
}

static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu)
{
	/*
	 * Check if our ASID is of an older version and thus invalid.
	 */

if (mm) {
		unsigned long asid = mm->context.asid[cpu];

if (asid == NO_CONTEXT ||
				((asid ^ cpu_asid_cache(cpu)) & ~ASID_MASK))
			get_new_mmu_context(mm, cpu);
	}
}

static inline void activate_context(struct mm_struct *mm, unsigned int cpu)
{
	get_mmu_context(mm, cpu);
	set_rasid_register(ASID_INSERT(mm->context.asid[cpu]));
	invalidate_page_directory();
}

/*
 * Initialize the context related info for a new mm_struct
 * instance.  Valid cpu values are 0..(NR_CPUS-1), so initializing
 * to -1 says the process has never run on any core.
 */

static inline int init_new_context(struct task_struct *tsk,
		struct mm_struct *mm)
{
	int cpu;
	for_each_possible_cpu(cpu) {
		mm->context.asid[cpu] = NO_CONTEXT;
	}
	mm->context.cpu = -1;
	return 0;
}

static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
			     struct task_struct *tsk)
{
	unsigned int cpu = smp_processor_id();
	int migrated = next->context.cpu != cpu;
	/* Flush the icache if we migrated to a new core. */
	if (migrated) {
		__invalidate_icache_all();
		next->context.cpu = cpu;
	}
	if (migrated || prev != next)
		activate_context(next, cpu);
}

#define activate_mm(prev, next)	switch_mm((prev), (next), NULL)
#define deactivate_mm(tsk, mm)	do { } while (0)

/*
 * Destroy context related info for an mm_struct that is about
 * to be put to rest.
 */
static inline void destroy_context(struct mm_struct *mm)
{
	invalidate_page_directory();
}

static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
{
	/* Nothing to do. */

}

#endif /* CONFIG_MMU */
#endif /* _XTENSA_MMU_CONTEXT_H */