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11/17/2022 06:42:16 AM
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Kbuild
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asm-offsets.h
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asm-uaccess.h
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asmmacro.h
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atomic.h
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barrier.h
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bitops.h
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bootparam.h
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cache.h
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cacheasm.h
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cacheflush.h
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checksum.h
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cmpxchg.h
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coprocessor.h
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delay.h
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elf.h
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highmem.h
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hw_breakpoint.h
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hw_irq.h
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initialize_mmu.h
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io.h
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irq.h
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irqflags.h
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kmem_layout.h
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mmu.h
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mmu_context.h
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module.h
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mxregs.h
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nommu_context.h
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pci-bridge.h
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pci.h
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perf_event.h
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pgalloc.h
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pgtable.h
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platform.h
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processor.h
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ptrace.h
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regs.h
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segment.h
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serial.h
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shmparam.h
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signal.h
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smp.h
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spinlock.h
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spinlock_types.h
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stacktrace.h
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string.h
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switch_to.h
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syscall.h
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sysmem.h
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thread_info.h
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timex.h
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tlb.h
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tlbflush.h
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traps.h
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types.h
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uaccess.h
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ucontext.h
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unaligned.h
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unistd.h
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user.h
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vectors.h
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vga.h
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Editing: mxregs.h
Close
/* * Xtensa MX interrupt distributor * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2008 - 2013 Tensilica Inc. */ #ifndef _XTENSA_MXREGS_H #define _XTENSA_MXREGS_H /* * RER/WER at, as Read/write external register * at: value * as: address * * Address Value * 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p * 0180 0...0m..m Clear enable specified by mask (m) * 0184 0...0m..m Set enable specified by mask (m) * 0190 0...0x..x 8-bit IPI partition register * VVVVVVVVPPPPUUUUUUUUUUUUUUUUU * V (10-bit) Release/Version * P ( 4-bit) Number of cores - 1 * U (18-bit) ID * 01a0 i.......i 32-bit ConfigID * 0200 0...0m..m RunStall core 'n' * 0220 c Cache coherency enabled */ #define MIROUT(irq) (0x000 + (irq)) #define MIPICAUSE(cpu) (0x100 + (cpu)) #define MIPISET(cause) (0x140 + (cause)) #define MIENG 0x180 #define MIENGSET 0x184 #define MIASG 0x188 /* Read Global Assert Register */ #define MIASGSET 0x18c /* Set Global Addert Regiter */ #define MIPIPART 0x190 #define SYSCFGID 0x1a0 #define MPSCORE 0x200 #define CCON 0x220 #endif /* _XTENSA_MXREGS_H */