OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 Kbuild	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	176 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 asm.h	1.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	11.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	2.59 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bitops.h	6.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	2.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	745 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	1.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat.h	924 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 csr.h	3.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	1.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	881 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fence.h	279 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 hwcap.h	1013 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	11.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	841 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	1.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	679 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	677 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	829 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	3.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	3.76 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pci.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	3.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-32.h	870 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-64.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-bits.h	1.81 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable.h	11.17 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 processor.h	2.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ptrace.h	2.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sbi.h	2.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	2.85 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 spinlock_types.h	906 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	838 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	1.86 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 syscall.h	2.59 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 thread_info.h	3.11 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 timex.h	1.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	717 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	1.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	14 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 unistd.h	638 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 word-at-a-time.h	1.48 KB	01/28/2018 09:20:33 PM	rw-r--r--

Name

Size

Modified

Perms

📁 ..

11/17/2022 06:42:16 AM

rwxr-xr-x

📄 Kbuild

1.37 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 asm-offsets.h

35 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 asm-prototypes.h

176 bytes

11/01/2022 04:52:05 PM

rw-r--r--

📄 asm.h

1.78 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 atomic.h

11.31 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 barrier.h

2.59 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 bitops.h

6.23 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bug.h

2.12 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cache.h

745 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 cacheflush.h

1.7 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cmpxchg.h

3.35 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 compat.h

924 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 csr.h

3.8 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 current.h

1.27 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 delay.h

881 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 dma-mapping.h

1.19 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 elf.h

2.3 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 fence.h

279 bytes

11/01/2022 04:52:05 PM

rw-r--r--

📄 hwcap.h

1013 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 io.h

11.81 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 irq.h

841 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 irqflags.h

1.54 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 kprobes.h

679 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 linkage.h

677 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu.h

829 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu_context.h

3.14 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 page.h

3.76 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 pci.h

1.16 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgalloc.h

3.06 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgtable-32.h

870 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgtable-64.h

2.08 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgtable-bits.h

1.81 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 pgtable.h

11.17 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 processor.h

2.44 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 ptrace.h

2.69 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 sbi.h

2.6 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 smp.h

1.59 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 spinlock.h

2.85 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 spinlock_types.h

906 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 string.h

838 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 switch_to.h

1.86 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 syscall.h

2.59 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 thread_info.h

3.11 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 timex.h

1.29 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 tlb.h

717 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 tlbflush.h

1.83 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 uaccess.h

14 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 unistd.h

638 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 vdso.h

1.49 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 word-at-a-time.h

1.48 KB

01/28/2018 09:20:33 PM

rw-r--r--

Editing: spinlock.h

/*
 * Copyright (C) 2015 Regents of the University of California
 * Copyright (C) 2017 SiFive
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 */

#ifndef _ASM_RISCV_SPINLOCK_H
#define _ASM_RISCV_SPINLOCK_H

#include <linux/kernel.h>
#include <asm/current.h>
#include <asm/fence.h>

/*
 * Simple spin lock operations.  These provide no fairness guarantees.
 */

/* FIXME: Replace this with a ticket lock, like MIPS. */

#define arch_spin_is_locked(x)	(READ_ONCE((x)->lock) != 0)

static inline void arch_spin_unlock(arch_spinlock_t *lock)
{
	smp_store_release(&lock->lock, 0);
}

static inline int arch_spin_trylock(arch_spinlock_t *lock)
{
	int tmp = 1, busy;

__asm__ __volatile__ (
		"	amoswap.w %0, %2, %1\n"
		RISCV_ACQUIRE_BARRIER
		: "=r" (busy), "+A" (lock->lock)
		: "r" (tmp)
		: "memory");

return !busy;
}

static inline void arch_spin_lock(arch_spinlock_t *lock)
{
	while (1) {
		if (arch_spin_is_locked(lock))
			continue;

if (arch_spin_trylock(lock))
			break;
	}
}

/***********************************************************/

static inline void arch_read_lock(arch_rwlock_t *lock)
{
	int tmp;

__asm__ __volatile__(
		"1:	lr.w	%1, %0\n"
		"	bltz	%1, 1b\n"
		"	addi	%1, %1, 1\n"
		"	sc.w	%1, %1, %0\n"
		"	bnez	%1, 1b\n"
		RISCV_ACQUIRE_BARRIER
		: "+A" (lock->lock), "=&r" (tmp)
		:: "memory");
}

static inline void arch_write_lock(arch_rwlock_t *lock)
{
	int tmp;

__asm__ __volatile__(
		"1:	lr.w	%1, %0\n"
		"	bnez	%1, 1b\n"
		"	li	%1, -1\n"
		"	sc.w	%1, %1, %0\n"
		"	bnez	%1, 1b\n"
		RISCV_ACQUIRE_BARRIER
		: "+A" (lock->lock), "=&r" (tmp)
		:: "memory");
}

static inline int arch_read_trylock(arch_rwlock_t *lock)
{
	int busy;

__asm__ __volatile__(
		"1:	lr.w	%1, %0\n"
		"	bltz	%1, 1f\n"
		"	addi	%1, %1, 1\n"
		"	sc.w	%1, %1, %0\n"
		"	bnez	%1, 1b\n"
		RISCV_ACQUIRE_BARRIER
		"1:\n"
		: "+A" (lock->lock), "=&r" (busy)
		:: "memory");

return !busy;
}

static inline int arch_write_trylock(arch_rwlock_t *lock)
{
	int busy;

__asm__ __volatile__(
		"1:	lr.w	%1, %0\n"
		"	bnez	%1, 1f\n"
		"	li	%1, -1\n"
		"	sc.w	%1, %1, %0\n"
		"	bnez	%1, 1b\n"
		RISCV_ACQUIRE_BARRIER
		"1:\n"
		: "+A" (lock->lock), "=&r" (busy)
		:: "memory");

return !busy;
}

static inline void arch_read_unlock(arch_rwlock_t *lock)
{
	__asm__ __volatile__(
		RISCV_RELEASE_BARRIER
		"	amoadd.w x0, %1, %0\n"
		: "+A" (lock->lock)
		: "r" (-1)
		: "memory");
}

static inline void arch_write_unlock(arch_rwlock_t *lock)
{
	smp_store_release(&lock->lock, 0);
}

#endif /* _ASM_RISCV_SPINLOCK_H */