OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 Kbuild	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	176 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 asm.h	1.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	11.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	2.59 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bitops.h	6.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	2.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	745 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	1.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat.h	924 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 csr.h	3.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	1.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	881 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fence.h	279 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 hwcap.h	1013 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	11.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	841 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	1.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	679 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	677 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	829 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	3.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	3.76 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pci.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	3.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-32.h	870 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-64.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-bits.h	1.81 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable.h	11.17 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 processor.h	2.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ptrace.h	2.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sbi.h	2.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	2.85 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 spinlock_types.h	906 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	838 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	1.86 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 syscall.h	2.59 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 thread_info.h	3.11 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 timex.h	1.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	717 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	1.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	14 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 unistd.h	638 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 word-at-a-time.h	1.48 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: mmu_context.h

/*
 * Copyright (C) 2012 Regents of the University of California
 * Copyright (C) 2017 SiFive
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 */

#ifndef _ASM_RISCV_MMU_CONTEXT_H
#define _ASM_RISCV_MMU_CONTEXT_H

#include <linux/mm_types.h>
#include <asm-generic/mm_hooks.h>

#include <linux/mm.h>
#include <linux/sched.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>

static inline void enter_lazy_tlb(struct mm_struct *mm,
	struct task_struct *task)
{
}

/* Initialize context-related info for a new mm_struct */
static inline int init_new_context(struct task_struct *task,
	struct mm_struct *mm)
{
	return 0;
}

static inline void destroy_context(struct mm_struct *mm)
{
}

static inline pgd_t *current_pgdir(void)
{
	return pfn_to_virt(csr_read(sptbr) & SPTBR_PPN);
}

static inline void set_pgdir(pgd_t *pgd)
{
	csr_write(sptbr, virt_to_pfn(pgd) | SPTBR_MODE);
}

/*
 * When necessary, performs a deferred icache flush for the given MM context,
 * on the local CPU.  RISC-V has no direct mechanism for instruction cache
 * shoot downs, so instead we send an IPI that informs the remote harts they
 * need to flush their local instruction caches.  To avoid pathologically slow
 * behavior in a common case (a bunch of single-hart processes on a many-hart
 * machine, ie 'make -j') we avoid the IPIs for harts that are not currently
 * executing a MM context and instead schedule a deferred local instruction
 * cache flush to be performed before execution resumes on each hart.  This
 * actually performs that local instruction cache flush, which implicitly only
 * refers to the current hart.
 */
static inline void flush_icache_deferred(struct mm_struct *mm)
{
#ifdef CONFIG_SMP
	unsigned int cpu = smp_processor_id();
	cpumask_t *mask = &mm->context.icache_stale_mask;

if (cpumask_test_cpu(cpu, mask)) {
		cpumask_clear_cpu(cpu, mask);
		/*
		 * Ensure the remote hart's writes are visible to this hart.
		 * This pairs with a barrier in flush_icache_mm.
		 */
		smp_mb();
		local_flush_icache_all();
	}
#endif
}

static inline void switch_mm(struct mm_struct *prev,
	struct mm_struct *next, struct task_struct *task)
{
	if (likely(prev != next)) {
		/*
		 * Mark the current MM context as inactive, and the next as
		 * active.  This is at least used by the icache flushing
		 * routines in order to determine who should
		 */
		unsigned int cpu = smp_processor_id();

cpumask_clear_cpu(cpu, mm_cpumask(prev));
		cpumask_set_cpu(cpu, mm_cpumask(next));

set_pgdir(next->pgd);
		local_flush_tlb_all();

flush_icache_deferred(next);
	}
}

static inline void activate_mm(struct mm_struct *prev,
			       struct mm_struct *next)
{
	switch_mm(prev, next, NULL);
}

static inline void deactivate_mm(struct task_struct *task,
	struct mm_struct *mm)
{
}

#endif /* _ASM_RISCV_MMU_CONTEXT_H */