OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 Kbuild	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	176 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 asm.h	1.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	11.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	2.59 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bitops.h	6.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	2.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	745 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	1.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat.h	924 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 csr.h	3.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	1.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	881 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fence.h	279 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 hwcap.h	1013 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	11.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	841 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	1.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	679 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	677 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	829 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	3.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	3.76 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pci.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	3.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-32.h	870 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-64.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-bits.h	1.81 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable.h	11.17 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 processor.h	2.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ptrace.h	2.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sbi.h	2.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	2.85 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 spinlock_types.h	906 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	838 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	1.86 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 syscall.h	2.59 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 thread_info.h	3.11 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 timex.h	1.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	717 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	1.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	14 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 unistd.h	638 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 word-at-a-time.h	1.48 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: bitops.h

/*
 * Copyright (C) 2012 Regents of the University of California
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 */

#ifndef _ASM_RISCV_BITOPS_H
#define _ASM_RISCV_BITOPS_H

#ifndef _LINUX_BITOPS_H
#error "Only <linux/bitops.h> can be included directly"
#endif /* _LINUX_BITOPS_H */

#include <linux/compiler.h>
#include <linux/irqflags.h>
#include <asm/barrier.h>
#include <asm/bitsperlong.h>

#ifndef smp_mb__before_clear_bit
#define smp_mb__before_clear_bit()  smp_mb()
#define smp_mb__after_clear_bit()   smp_mb()
#endif /* smp_mb__before_clear_bit */

#include <asm-generic/bitops/__ffs.h>
#include <asm-generic/bitops/ffz.h>
#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/find.h>
#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/ffs.h>

#include <asm-generic/bitops/hweight.h>

#if (BITS_PER_LONG == 64)
#define __AMO(op)	"amo" #op ".d"
#elif (BITS_PER_LONG == 32)
#define __AMO(op)	"amo" #op ".w"
#else
#error "Unexpected BITS_PER_LONG"
#endif

#define __test_and_op_bit_ord(op, mod, nr, addr, ord)		\
({								\
	unsigned long __res, __mask;				\
	__mask = BIT_MASK(nr);					\
	__asm__ __volatile__ (					\
		__AMO(op) #ord " %0, %2, %1"			\
		: "=r" (__res), "+A" (addr[BIT_WORD(nr)])	\
		: "r" (mod(__mask))				\
		: "memory");					\
	((__res & __mask) != 0);				\
})

#define __op_bit_ord(op, mod, nr, addr, ord)			\
	__asm__ __volatile__ (					\
		__AMO(op) #ord " zero, %1, %0"			\
		: "+A" (addr[BIT_WORD(nr)])			\
		: "r" (mod(BIT_MASK(nr)))			\
		: "memory");

#define __test_and_op_bit(op, mod, nr, addr) 			\
	__test_and_op_bit_ord(op, mod, nr, addr, .aqrl)
#define __op_bit(op, mod, nr, addr)				\
	__op_bit_ord(op, mod, nr, addr, )

/* Bitmask modifiers */
#define __NOP(x)	(x)
#define __NOT(x)	(~(x))

/**
 * test_and_set_bit - Set a bit and return its old value
 * @nr: Bit to set
 * @addr: Address to count from
 *
 * This operation may be reordered on other architectures than x86.
 */
static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
{
	return __test_and_op_bit(or, __NOP, nr, addr);
}

/**
 * test_and_clear_bit - Clear a bit and return its old value
 * @nr: Bit to clear
 * @addr: Address to count from
 *
 * This operation can be reordered on other architectures other than x86.
 */
static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
{
	return __test_and_op_bit(and, __NOT, nr, addr);
}

/**
 * test_and_change_bit - Change a bit and return its old value
 * @nr: Bit to change
 * @addr: Address to count from
 *
 * This operation is atomic and cannot be reordered.
 * It also implies a memory barrier.
 */
static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
{
	return __test_and_op_bit(xor, __NOP, nr, addr);
}

/**
 * set_bit - Atomically set a bit in memory
 * @nr: the bit to set
 * @addr: the address to start counting from
 *
 * Note: there are no guarantees that this function will not be reordered
 * on non x86 architectures, so if you are writing portable code,
 * make sure not to rely on its reordering guarantees.
 *
 * Note that @nr may be almost arbitrarily large; this function is not
 * restricted to acting on a single-word quantity.
 */
static inline void set_bit(int nr, volatile unsigned long *addr)
{
	__op_bit(or, __NOP, nr, addr);
}

/**
 * clear_bit - Clears a bit in memory
 * @nr: Bit to clear
 * @addr: Address to start counting from
 *
 * Note: there are no guarantees that this function will not be reordered
 * on non x86 architectures, so if you are writing portable code,
 * make sure not to rely on its reordering guarantees.
 */
static inline void clear_bit(int nr, volatile unsigned long *addr)
{
	__op_bit(and, __NOT, nr, addr);
}

/**
 * change_bit - Toggle a bit in memory
 * @nr: Bit to change
 * @addr: Address to start counting from
 *
 * change_bit()  may be reordered on other architectures than x86.
 * Note that @nr may be almost arbitrarily large; this function is not
 * restricted to acting on a single-word quantity.
 */
static inline void change_bit(int nr, volatile unsigned long *addr)
{
	__op_bit(xor, __NOP, nr, addr);
}

/**
 * test_and_set_bit_lock - Set a bit and return its old value, for lock
 * @nr: Bit to set
 * @addr: Address to count from
 *
 * This operation is atomic and provides acquire barrier semantics.
 * It can be used to implement bit locks.
 */
static inline int test_and_set_bit_lock(
	unsigned long nr, volatile unsigned long *addr)
{
	return __test_and_op_bit_ord(or, __NOP, nr, addr, .aq);
}

/**
 * clear_bit_unlock - Clear a bit in memory, for unlock
 * @nr: the bit to set
 * @addr: the address to start counting from
 *
 * This operation is atomic and provides release barrier semantics.
 */
static inline void clear_bit_unlock(
	unsigned long nr, volatile unsigned long *addr)
{
	__op_bit_ord(and, __NOT, nr, addr, .rl);
}

/**
 * __clear_bit_unlock - Clear a bit in memory, for unlock
 * @nr: the bit to set
 * @addr: the address to start counting from
 *
 * This operation is like clear_bit_unlock, however it is not atomic.
 * It does provide release barrier semantics so it can be used to unlock
 * a bit lock, however it would only be used if no other CPU can modify
 * any bits in the memory until the lock is released (a good example is
 * if the bit lock itself protects access to the other bits in the word).
 *
 * On RISC-V systems there seems to be no benefit to taking advantage of the
 * non-atomic property here: it's a lot more instructions and we still have to
 * provide release semantics anyway.
 */
static inline void __clear_bit_unlock(
	unsigned long nr, volatile unsigned long *addr)
{
	clear_bit_unlock(nr, addr);
}

#undef __test_and_op_bit
#undef __op_bit
#undef __NOP
#undef __NOT
#undef __AMO

#include <asm-generic/bitops/non-atomic.h>
#include <asm-generic/bitops/le.h>
#include <asm-generic/bitops/ext2-atomic.h>

#endif /* _ASM_RISCV_BITOPS_H */