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11/17/2022 06:42:16 AM
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Kbuild
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asm-offsets.h
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asm-prototypes.h
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asm.h
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atomic.h
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barrier.h
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bitops.h
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fence.h
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spinlock.h
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word-at-a-time.h
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Editing: barrier.h
Close
/* * Based on arch/arm/include/asm/barrier.h * * Copyright (C) 2012 ARM Ltd. * Copyright (C) 2013 Regents of the University of California * Copyright (C) 2017 SiFive * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #ifndef _ASM_RISCV_BARRIER_H #define _ASM_RISCV_BARRIER_H #ifndef __ASSEMBLY__ #define nop() __asm__ __volatile__ ("nop") #define RISCV_FENCE(p, s) \ __asm__ __volatile__ ("fence " #p "," #s : : : "memory") /* These barriers need to enforce ordering on both devices or memory. */ #define mb() RISCV_FENCE(iorw,iorw) #define rmb() RISCV_FENCE(ir,ir) #define wmb() RISCV_FENCE(ow,ow) /* These barriers do not need to enforce ordering on devices, just memory. */ #define smp_mb() RISCV_FENCE(rw,rw) #define smp_rmb() RISCV_FENCE(r,r) #define smp_wmb() RISCV_FENCE(w,w) /* * This is a very specific barrier: it's currently only used in two places in * the kernel, both in the scheduler. See include/linux/spinlock.h for the two * orderings it guarantees, but the "critical section is RCsc" guarantee * mandates a barrier on RISC-V. The sequence looks like: * * lr.aq lock * sc lock <= LOCKED * smp_mb__after_spinlock() * // critical section * lr lock * sc.rl lock <= UNLOCKED * * The AQ/RL pair provides a RCpc critical section, but there's not really any * way we can take advantage of that here because the ordering is only enforced * on that one lock. Thus, we're just doing a full fence. * * Since we allow writeX to be called from preemptive regions we need at least * an "o" in the predecessor set to ensure device writes are visible before the * task is marked as available for scheduling on a new hart. While I don't see * any concrete reason we need a full IO fence, it seems safer to just upgrade * this in order to avoid any IO crossing a scheduling boundary. In both * instances the scheduler pairs this with an mb(), so nothing is necessary on * the new hart. */ #define smp_mb__after_spinlock() RISCV_FENCE(iorw,iorw) #include <asm-generic/barrier.h> #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_BARRIER_H */