OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 Kbuild	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	176 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 asm.h	1.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	11.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	2.59 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bitops.h	6.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	2.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	745 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	1.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat.h	924 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 csr.h	3.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	1.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	881 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fence.h	279 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 hwcap.h	1013 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	11.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	841 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	1.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	679 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	677 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	829 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	3.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	3.76 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pci.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	3.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-32.h	870 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-64.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-bits.h	1.81 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable.h	11.17 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 processor.h	2.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ptrace.h	2.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sbi.h	2.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	2.85 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 spinlock_types.h	906 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	838 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	1.86 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 syscall.h	2.59 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 thread_info.h	3.11 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 timex.h	1.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	717 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	1.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	14 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 unistd.h	638 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 word-at-a-time.h	1.48 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: csr.h

/*
 * Copyright (C) 2015 Regents of the University of California
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 */

#ifndef _ASM_RISCV_CSR_H
#define _ASM_RISCV_CSR_H

#include <linux/const.h>

/* Status register flags */
#define SR_SIE	_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
#define SR_SPIE	_AC(0x00000020, UL) /* Previous Supervisor IE */
#define SR_SPP	_AC(0x00000100, UL) /* Previously Supervisor */
#define SR_SUM	_AC(0x00040000, UL) /* Supervisor may access User Memory */

#define SR_FS           _AC(0x00006000, UL) /* Floating-point Status */
#define SR_FS_OFF       _AC(0x00000000, UL)
#define SR_FS_INITIAL   _AC(0x00002000, UL)
#define SR_FS_CLEAN     _AC(0x00004000, UL)
#define SR_FS_DIRTY     _AC(0x00006000, UL)

#define SR_XS           _AC(0x00018000, UL) /* Extension Status */
#define SR_XS_OFF       _AC(0x00000000, UL)
#define SR_XS_INITIAL   _AC(0x00008000, UL)
#define SR_XS_CLEAN     _AC(0x00010000, UL)
#define SR_XS_DIRTY     _AC(0x00018000, UL)

#ifndef CONFIG_64BIT
#define SR_SD   _AC(0x80000000, UL) /* FS/XS dirty */
#else
#define SR_SD   _AC(0x8000000000000000, UL) /* FS/XS dirty */
#endif

/* SPTBR flags */
#if __riscv_xlen == 32
#define SPTBR_PPN     _AC(0x003FFFFF, UL)
#define SPTBR_MODE_32 _AC(0x80000000, UL)
#define SPTBR_MODE    SPTBR_MODE_32
#else
#define SPTBR_PPN     _AC(0x00000FFFFFFFFFFF, UL)
#define SPTBR_MODE_39 _AC(0x8000000000000000, UL)
#define SPTBR_MODE    SPTBR_MODE_39
#endif

/* Interrupt Enable and Interrupt Pending flags */
#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */
#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */

#define EXC_INST_MISALIGNED     0
#define EXC_INST_ACCESS         1
#define EXC_BREAKPOINT          3
#define EXC_LOAD_ACCESS         5
#define EXC_STORE_ACCESS        7
#define EXC_SYSCALL             8
#define EXC_INST_PAGE_FAULT     12
#define EXC_LOAD_PAGE_FAULT     13
#define EXC_STORE_PAGE_FAULT    15

#ifndef __ASSEMBLY__

#define csr_swap(csr, val)					\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrrw %0, " #csr ", %1"		\
			      : "=r" (__v) : "rK" (__v)		\
			      : "memory");			\
	__v;							\
})

#define csr_read(csr)						\
({								\
	register unsigned long __v;				\
	__asm__ __volatile__ ("csrr %0, " #csr			\
			      : "=r" (__v) :			\
			      : "memory");			\
	__v;							\
})

#define csr_write(csr, val)					\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrw " #csr ", %0"		\
			      : : "rK" (__v)			\
			      : "memory");			\
})

#define csr_read_set(csr, val)					\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrrs %0, " #csr ", %1"		\
			      : "=r" (__v) : "rK" (__v)		\
			      : "memory");			\
	__v;							\
})

#define csr_set(csr, val)					\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrs " #csr ", %0"		\
			      : : "rK" (__v)			\
			      : "memory");			\
})

#define csr_read_clear(csr, val)				\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrrc %0, " #csr ", %1"		\
			      : "=r" (__v) : "rK" (__v)		\
			      : "memory");			\
	__v;							\
})

#define csr_clear(csr, val)					\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrc " #csr ", %0"		\
			      : : "rK" (__v)			\
			      : "memory");			\
})

#endif /* __ASSEMBLY__ */

#endif /* _ASM_RISCV_CSR_H */