OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 Kbuild	467 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 adc.h	253 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 addrspace.h	2.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 alignment.h	654 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic-grb.h	2.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic-irq.h	1.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic-llsc.h	2.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	1.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	1.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops-cas.h	1.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops-grb.h	6.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops-llsc.h	2.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops-op32.h	3.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	2.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bl_bit.h	216 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bl_bit_32.h	639 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bl_bit_64.h	979 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	2.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	1.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	1.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache_insns.h	242 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache_insns_32.h	642 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache_insns_64.h	839 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	3.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	140 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum_32.h	5.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clock.h	436 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg-cas.h	549 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg-grb.h	2.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg-irq.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg-llsc.h	1.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg-xchg.h	1.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	1.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 device.h	450 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	694 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-register.h	1.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	3.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dmabrg.h	536 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dwarf.h	9.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	7.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 entry-macros.S	1.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable.h	227 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	375 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flat.h	1.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu.h	1.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 freq.h	472 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex-cas.h	728 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex-irq.h	482 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex-llsc.h	870 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	1.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gpio.h	1017 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	440 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hd64461.h	11.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 heartbeat.h	383 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb.h	1.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_breakpoint.h	1.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	915 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-sh7760.h	406 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	11.33 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 io_generic.h	661 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io_noioport.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io_trapped.h	1.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	226 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug.h	406 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	2.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	851 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	265 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	1.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	154 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 machvec.h	939 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	2.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	4.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context_32.h	1.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context_64.h	1.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	1005 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	6.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	3.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	797 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	1.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-2level.h	598 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-3level.h	1.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable_32.h	16.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable_64.h	11.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 posix_types.h	146 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	4.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor_32.h	4.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor_64.h	5.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	3.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace_32.h	307 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace_64.h	312 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 push-switch.h	755 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 reboot.h	472 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 romimage-macros.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rtc.h	383 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 seccomp.h	280 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	307 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 segment.h	879 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	725 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sfp-machine.h	3.43 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 sh7760fb.h	5.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sh_bios.h	743 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	629 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 siu.h	539 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smc37c93x.h	5.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp-ops.h	1012 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	1.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sparsemem.h	443 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spi.h	265 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock-cas.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock-llsc.h	4.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	578 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	463 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sram.h	670 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackprotector.h	711 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	606 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	131 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string_32.h	2.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string_64.h	499 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 suspend.h	2.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	492 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to_32.h	3.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to_64.h	968 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	267 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall_32.h	2.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall_64.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscalls.h	564 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscalls_32.h	1022 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscalls_64.h	441 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	5.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	637 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	4.12 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tlb_64.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	1.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	645 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	487 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps_32.h	1.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps_64.h	851 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 types.h	411 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	4.83 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 uaccess_32.h	3.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess_64.h	2.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned-sh4a.h	4.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	359 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uncached.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	952 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unwinder.h	856 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	2.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	98 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vmlinux.lds.h	558 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 watchdog.h	4.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 word-at-a-time.h	1.29 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: io.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_SH_IO_H
#define __ASM_SH_IO_H

/*
 * Convention:
 *    read{b,w,l,q}/write{b,w,l,q} are for PCI,
 *    while in{b,w,l}/out{b,w,l} are for ISA
 *
 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
 * and 'string' versions: ins{b,w,l}/outs{b,w,l}
 *
 * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
 * automatically, there are also __raw versions, which do not.
 */
#include <linux/errno.h>
#include <asm/cache.h>
#include <asm/addrspace.h>
#include <asm/machvec.h>
#include <asm/pgtable.h>
#include <asm-generic/iomap.h>

#ifdef __KERNEL__
#define __IO_PREFIX     generic
#include <asm/io_generic.h>
#include <asm/io_trapped.h>
#include <mach/mangle-port.h>

#define __raw_writeb(v,a)	(__chk_io_ptr(a), *(volatile u8  __force *)(a) = (v))
#define __raw_writew(v,a)	(__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
#define __raw_writel(v,a)	(__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
#define __raw_writeq(v,a)	(__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v))

#define __raw_readb(a)		(__chk_io_ptr(a), *(volatile u8  __force *)(a))
#define __raw_readw(a)		(__chk_io_ptr(a), *(volatile u16 __force *)(a))
#define __raw_readl(a)		(__chk_io_ptr(a), *(volatile u32 __force *)(a))
#define __raw_readq(a)		(__chk_io_ptr(a), *(volatile u64 __force *)(a))

#define readb_relaxed(c)	({ u8  __v = ioswabb(__raw_readb(c)); __v; })
#define readw_relaxed(c)	({ u16 __v = ioswabw(__raw_readw(c)); __v; })
#define readl_relaxed(c)	({ u32 __v = ioswabl(__raw_readl(c)); __v; })
#define readq_relaxed(c)	({ u64 __v = ioswabq(__raw_readq(c)); __v; })

#define writeb_relaxed(v,c)	((void)__raw_writeb((__force  u8)ioswabb(v),c))
#define writew_relaxed(v,c)	((void)__raw_writew((__force u16)ioswabw(v),c))
#define writel_relaxed(v,c)	((void)__raw_writel((__force u32)ioswabl(v),c))
#define writeq_relaxed(v,c)	((void)__raw_writeq((__force u64)ioswabq(v),c))

#define readb(a)		({ u8  r_ = readb_relaxed(a); rmb(); r_; })
#define readw(a)		({ u16 r_ = readw_relaxed(a); rmb(); r_; })
#define readl(a)		({ u32 r_ = readl_relaxed(a); rmb(); r_; })
#define readq(a)		({ u64 r_ = readq_relaxed(a); rmb(); r_; })

#define writeb(v,a)		({ wmb(); writeb_relaxed((v),(a)); })
#define writew(v,a)		({ wmb(); writew_relaxed((v),(a)); })
#define writel(v,a)		({ wmb(); writel_relaxed((v),(a)); })
#define writeq(v,a)		({ wmb(); writeq_relaxed((v),(a)); })

#define readsb(p,d,l)		__raw_readsb(p,d,l)
#define readsw(p,d,l)		__raw_readsw(p,d,l)
#define readsl(p,d,l)		__raw_readsl(p,d,l)

#define writesb(p,d,l)		__raw_writesb(p,d,l)
#define writesw(p,d,l)		__raw_writesw(p,d,l)
#define writesl(p,d,l)		__raw_writesl(p,d,l)

#define __BUILD_UNCACHED_IO(bwlq, type)					\
static inline type read##bwlq##_uncached(unsigned long addr)		\
{									\
	type ret;							\
	jump_to_uncached();						\
	ret = __raw_read##bwlq(addr);					\
	back_to_cached();						\
	return ret;							\
}									\
									\
static inline void write##bwlq##_uncached(type v, unsigned long addr)	\
{									\
	jump_to_uncached();						\
	__raw_write##bwlq(v, addr);					\
	back_to_cached();						\
}

__BUILD_UNCACHED_IO(b, u8)
__BUILD_UNCACHED_IO(w, u16)
__BUILD_UNCACHED_IO(l, u32)
__BUILD_UNCACHED_IO(q, u64)

#define __BUILD_MEMORY_STRING(pfx, bwlq, type)				\
									\
static inline void							\
pfx##writes##bwlq(volatile void __iomem *mem, const void *addr,		\
		  unsigned int count)					\
{									\
	const volatile type *__addr = addr;				\
									\
	while (count--) {						\
		__raw_write##bwlq(*__addr, mem);			\
		__addr++;						\
	}								\
}									\
									\
static inline void pfx##reads##bwlq(volatile void __iomem *mem,		\
				    void *addr, unsigned int count)	\
{									\
	volatile type *__addr = addr;					\
									\
	while (count--) {						\
		*__addr = __raw_read##bwlq(mem);			\
		__addr++;						\
	}								\
}

__BUILD_MEMORY_STRING(__raw_, b, u8)
__BUILD_MEMORY_STRING(__raw_, w, u16)

#ifdef CONFIG_SUPERH32
void __raw_writesl(void __iomem *addr, const void *data, int longlen);
void __raw_readsl(const void __iomem *addr, void *data, int longlen);
#else
__BUILD_MEMORY_STRING(__raw_, l, u32)
#endif

__BUILD_MEMORY_STRING(__raw_, q, u64)

#ifdef CONFIG_HAS_IOPORT_MAP

/*
 * Slowdown I/O port space accesses for antique hardware.
 */
#undef CONF_SLOWDOWN_IO

/*
 * On SuperH I/O ports are memory mapped, so we access them using normal
 * load/store instructions. sh_io_port_base is the virtual address to
 * which all ports are being mapped.
 */
extern unsigned long sh_io_port_base;

static inline void __set_io_port_base(unsigned long pbase)
{
	*(unsigned long *)&sh_io_port_base = pbase;
	barrier();
}

#ifdef CONFIG_GENERIC_IOMAP
#define __ioport_map ioport_map
#else
extern void __iomem *__ioport_map(unsigned long addr, unsigned int size);
#endif

#ifdef CONF_SLOWDOWN_IO
#define SLOW_DOWN_IO __raw_readw(sh_io_port_base)
#else
#define SLOW_DOWN_IO
#endif

#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)			\
									\
static inline void pfx##out##bwlq##p(type val, unsigned long port)	\
{									\
	volatile type *__addr;						\
									\
	__addr = __ioport_map(port, sizeof(type));			\
	*__addr = val;							\
	slow;								\
}									\
									\
static inline type pfx##in##bwlq##p(unsigned long port)			\
{									\
	volatile type *__addr;						\
	type __val;							\
									\
	__addr = __ioport_map(port, sizeof(type));			\
	__val = *__addr;						\
	slow;								\
									\
	return __val;							\
}

#define __BUILD_IOPORT_PFX(bus, bwlq, type)				\
	__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)			\
	__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)

#define BUILDIO_IOPORT(bwlq, type)					\
	__BUILD_IOPORT_PFX(, bwlq, type)

BUILDIO_IOPORT(b, u8)
BUILDIO_IOPORT(w, u16)
BUILDIO_IOPORT(l, u32)
BUILDIO_IOPORT(q, u64)

#define __BUILD_IOPORT_STRING(bwlq, type)				\
									\
static inline void outs##bwlq(unsigned long port, const void *addr,	\
			      unsigned int count)			\
{									\
	const volatile type *__addr = addr;				\
									\
	while (count--) {						\
		out##bwlq(*__addr, port);				\
		__addr++;						\
	}								\
}									\
									\
static inline void ins##bwlq(unsigned long port, void *addr,		\
			     unsigned int count)			\
{									\
	volatile type *__addr = addr;					\
									\
	while (count--) {						\
		*__addr = in##bwlq(port);				\
		__addr++;						\
	}								\
}

__BUILD_IOPORT_STRING(b, u8)
__BUILD_IOPORT_STRING(w, u16)
__BUILD_IOPORT_STRING(l, u32)
__BUILD_IOPORT_STRING(q, u64)

#else /* !CONFIG_HAS_IOPORT_MAP */

#include <asm/io_noioport.h>

#endif

#define IO_SPACE_LIMIT 0xffffffff

/* synco on SH-4A, otherwise a nop */
#define mmiowb()		wmb()

/* We really want to try and get these to memcpy etc */
void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
void memset_io(volatile void __iomem *, int, unsigned long);

/* Quad-word real-mode I/O, don't ask.. */
unsigned long long peek_real_address_q(unsigned long long addr);
unsigned long long poke_real_address_q(unsigned long long addr,
				       unsigned long long val);

#if !defined(CONFIG_MMU)
#define virt_to_phys(address)	((unsigned long)(address))
#define phys_to_virt(address)	((void *)(address))
#else
#define virt_to_phys(address)	(__pa(address))
#define phys_to_virt(address)	(__va(address))
#endif

/*
 * On 32-bit SH, we traditionally have the whole physical address space
 * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
 * not need to do anything but place the address in the proper segment.
 * This is true for P1 and P2 addresses, as well as some P3 ones.
 * However, most of the P3 addresses and newer cores using extended
 * addressing need to map through page tables, so the ioremap()
 * implementation becomes a bit more complicated.
 *
 * See arch/sh/mm/ioremap.c for additional notes on this.
 *
 * We cheat a bit and always return uncachable areas until we've fixed
 * the drivers to handle caching properly.
 *
 * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
 * doesn't exist, so everything must go through page tables.
 */
#ifdef CONFIG_MMU
void __iomem *__ioremap_caller(phys_addr_t offset, unsigned long size,
			       pgprot_t prot, void *caller);
void __iounmap(void __iomem *addr);

static inline void __iomem *
__ioremap(phys_addr_t offset, unsigned long size, pgprot_t prot)
{
	return __ioremap_caller(offset, size, prot, __builtin_return_address(0));
}

static inline void __iomem *
__ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot)
{
#ifdef CONFIG_29BIT
	phys_addr_t last_addr = offset + size - 1;

/*
	 * For P1 and P2 space this is trivial, as everything is already
	 * mapped. Uncached access for P1 addresses are done through P2.
	 * In the P3 case or for addresses outside of the 29-bit space,
	 * mapping must be done by the PMB or by using page tables.
	 */
	if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
		u64 flags = pgprot_val(prot);

/*
		 * Anything using the legacy PTEA space attributes needs
		 * to be kicked down to page table mappings.
		 */
		if (unlikely(flags & _PAGE_PCC_MASK))
			return NULL;
		if (unlikely(flags & _PAGE_CACHABLE))
			return (void __iomem *)P1SEGADDR(offset);

return (void __iomem *)P2SEGADDR(offset);
	}

/* P4 above the store queues are always mapped. */
	if (unlikely(offset >= P3_ADDR_MAX))
		return (void __iomem *)P4SEGADDR(offset);
#endif

return NULL;
}

static inline void __iomem *
__ioremap_mode(phys_addr_t offset, unsigned long size, pgprot_t prot)
{
	void __iomem *ret;

ret = __ioremap_trapped(offset, size);
	if (ret)
		return ret;

ret = __ioremap_29bit(offset, size, prot);
	if (ret)
		return ret;

return __ioremap(offset, size, prot);
}
#else
#define __ioremap(offset, size, prot)		((void __iomem *)(offset))
#define __ioremap_mode(offset, size, prot)	((void __iomem *)(offset))
#define __iounmap(addr)				do { } while (0)
#endif /* CONFIG_MMU */

static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
{
	return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE);
}

static inline void __iomem *
ioremap_cache(phys_addr_t offset, unsigned long size)
{
	return __ioremap_mode(offset, size, PAGE_KERNEL);
}
#define ioremap_cache ioremap_cache

#ifdef CONFIG_HAVE_IOREMAP_PROT
static inline void __iomem *
ioremap_prot(phys_addr_t offset, unsigned long size, unsigned long flags)
{
	return __ioremap_mode(offset, size, __pgprot(flags));
}
#endif

#ifdef CONFIG_IOREMAP_FIXED
extern void __iomem *ioremap_fixed(phys_addr_t, unsigned long, pgprot_t);
extern int iounmap_fixed(void __iomem *);
extern void ioremap_fixed_init(void);
#else
static inline void __iomem *
ioremap_fixed(phys_addr_t phys_addr, unsigned long size, pgprot_t prot)
{
	BUG();
	return NULL;
}

static inline void ioremap_fixed_init(void) { }
static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; }
#endif

#define ioremap_nocache	ioremap
#define ioremap_uc	ioremap

static inline void iounmap(void __iomem *addr)
{
	__iounmap(addr);
}

/*
 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 * access
 */
#define xlate_dev_mem_ptr(p)	__va(p)

/*
 * Convert a virtual cached pointer to an uncached pointer
 */
#define xlate_dev_kmem_ptr(p)	p

#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
int valid_phys_addr_range(phys_addr_t addr, size_t size);
int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);

#endif /* __KERNEL__ */

#endif /* __ASM_SH_IO_H */