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linux-headers-4.15.0-197
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powerpc
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include
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asm
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Size
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11/17/2022 06:42:16 AM
rwxr-xr-x
📄
8xx_immap.h
13.77 KB
01/28/2018 09:20:33 PM
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📄
Kbuild
248 bytes
01/28/2018 09:20:33 PM
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accounting.h
1 KB
01/28/2018 09:20:33 PM
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agp.h
525 bytes
01/28/2018 09:20:33 PM
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archrandom.h
1016 bytes
11/01/2022 04:52:05 PM
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asm-compat.h
2.53 KB
01/28/2018 09:20:33 PM
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asm-offsets.h
35 bytes
01/28/2018 09:20:33 PM
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asm-prototypes.h
4.78 KB
11/01/2022 04:52:05 PM
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async_tx.h
1.64 KB
01/28/2018 09:20:33 PM
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atomic.h
13.57 KB
01/28/2018 09:20:33 PM
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backlight.h
1.09 KB
01/28/2018 09:20:33 PM
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barrier.h
3.57 KB
11/01/2022 04:52:05 PM
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bitops.h
7.8 KB
11/01/2022 04:52:05 PM
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book3s
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11/17/2022 06:42:21 AM
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bootx.h
1.12 KB
01/28/2018 09:20:33 PM
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btext.h
926 bytes
01/28/2018 09:20:33 PM
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bug.h
3.55 KB
01/28/2018 09:20:33 PM
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bugs.h
486 bytes
01/28/2018 09:20:33 PM
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cache.h
2.47 KB
11/01/2022 04:52:05 PM
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cacheflush.h
3.76 KB
01/28/2018 09:20:33 PM
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cell-pmu.h
4.04 KB
01/28/2018 09:20:33 PM
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cell-regs.h
9.57 KB
01/28/2018 09:20:33 PM
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checksum.h
5.85 KB
01/28/2018 09:20:33 PM
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cmpxchg.h
12.16 KB
01/28/2018 09:20:33 PM
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📄
code-patching-asm.h
397 bytes
11/01/2022 04:52:05 PM
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code-patching.h
5.01 KB
11/01/2022 04:52:05 PM
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compat.h
6.26 KB
01/28/2018 09:20:33 PM
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context_tracking.h
245 bytes
01/28/2018 09:20:33 PM
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copro.h
769 bytes
01/28/2018 09:20:33 PM
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cpm.h
5.09 KB
01/28/2018 09:20:33 PM
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cpm1.h
21.08 KB
01/28/2018 09:20:33 PM
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cpm2.h
48.43 KB
01/28/2018 09:20:33 PM
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cpu_has_feature.h
1.31 KB
11/01/2022 04:52:05 PM
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cpufeature.h
1.18 KB
01/28/2018 09:20:33 PM
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cpuidle.h
3.31 KB
01/28/2018 09:20:33 PM
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cputable.h
22.56 KB
11/01/2022 04:52:05 PM
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cputhreads.h
2.92 KB
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cputime.h
1.59 KB
01/28/2018 09:20:33 PM
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current.h
835 bytes
01/28/2018 09:20:33 PM
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dbdma.h
3.72 KB
01/28/2018 09:20:33 PM
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dbell.h
2.78 KB
01/28/2018 09:20:33 PM
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dcr-generic.h
1.58 KB
01/28/2018 09:20:33 PM
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dcr-mmio.h
1.68 KB
01/28/2018 09:20:33 PM
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dcr-native.h
4.42 KB
11/01/2022 04:52:05 PM
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dcr-regs.h
5.71 KB
01/28/2018 09:20:33 PM
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dcr.h
2.73 KB
01/28/2018 09:20:33 PM
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debug.h
1.97 KB
01/28/2018 09:20:33 PM
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debugfs.h
489 bytes
01/28/2018 09:20:33 PM
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delay.h
3.42 KB
01/28/2018 09:20:33 PM
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device.h
1.1 KB
01/28/2018 09:20:33 PM
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disassemble.h
2.73 KB
01/28/2018 09:20:33 PM
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dma-mapping.h
4.12 KB
01/28/2018 09:20:33 PM
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dma.h
10.51 KB
01/28/2018 09:20:33 PM
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dt_cpu_ftrs.h
816 bytes
01/28/2018 09:20:33 PM
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edac.h
1.08 KB
01/28/2018 09:20:33 PM
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eeh.h
14.44 KB
01/28/2018 09:20:33 PM
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eeh_event.h
1.36 KB
01/28/2018 09:20:33 PM
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ehv_pic.h
963 bytes
01/28/2018 09:20:33 PM
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elf.h
6.29 KB
01/28/2018 09:20:33 PM
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emergency-restart.h
43 bytes
01/28/2018 09:20:33 PM
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emulated_ops.h
2.58 KB
01/28/2018 09:20:33 PM
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epapr_hcalls.h
16.44 KB
01/28/2018 09:20:33 PM
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exception-64e.h
7.21 KB
01/28/2018 09:20:33 PM
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exception-64s.h
22.72 KB
11/01/2022 04:52:05 PM
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exec.h
246 bytes
01/28/2018 09:20:33 PM
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extable.h
904 bytes
01/28/2018 09:20:33 PM
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fadump.h
6.1 KB
11/01/2022 04:52:05 PM
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fb.h
483 bytes
01/28/2018 09:20:33 PM
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📄
feature-fixups.h
8.76 KB
11/01/2022 04:52:05 PM
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📄
firmware.h
4.71 KB
01/28/2018 09:20:33 PM
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📄
fixmap.h
2.33 KB
01/28/2018 09:20:33 PM
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📄
floppy.h
4.86 KB
01/28/2018 09:20:33 PM
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📄
fs_pd.h
1.02 KB
01/28/2018 09:20:33 PM
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📄
fsl_85xx_cache_sram.h
1.43 KB
01/28/2018 09:20:33 PM
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📄
fsl_gtm.h
1.38 KB
01/28/2018 09:20:33 PM
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📄
fsl_hcalls.h
17.2 KB
01/28/2018 09:20:33 PM
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📄
fsl_lbc.h
10.9 KB
01/28/2018 09:20:33 PM
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fsl_pamu_stash.h
1.1 KB
01/28/2018 09:20:33 PM
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📄
fsl_pm.h
1.36 KB
01/28/2018 09:20:33 PM
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📄
ftrace.h
2.1 KB
01/28/2018 09:20:33 PM
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📄
futex.h
2.4 KB
11/01/2022 04:52:05 PM
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grackle.h
331 bytes
01/28/2018 09:20:33 PM
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hardirq.h
1.15 KB
01/28/2018 09:20:33 PM
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head-64.h
13.86 KB
01/28/2018 09:20:33 PM
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heathrow.h
2.53 KB
01/28/2018 09:20:33 PM
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highmem.h
2.41 KB
01/28/2018 09:20:33 PM
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📄
hmi.h
1.49 KB
11/01/2022 04:52:05 PM
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📄
hugetlb.h
4.73 KB
11/01/2022 04:52:05 PM
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hvcall.h
15.35 KB
11/01/2022 04:52:05 PM
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📄
hvconsole.h
1.37 KB
01/28/2018 09:20:33 PM
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hvcserver.h
2.09 KB
01/28/2018 09:20:33 PM
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📄
hvsi.h
2.78 KB
01/28/2018 09:20:33 PM
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hw_breakpoint.h
3.07 KB
01/28/2018 09:20:33 PM
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hw_irq.h
5.24 KB
11/01/2022 04:52:05 PM
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📄
hydra.h
2.91 KB
01/28/2018 09:20:33 PM
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📄
i8259.h
361 bytes
01/28/2018 09:20:33 PM
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📄
ibmebus.h
2.15 KB
01/28/2018 09:20:33 PM
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📄
icswx.h
4.71 KB
01/28/2018 09:20:33 PM
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📄
ide.h
586 bytes
01/28/2018 09:20:33 PM
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📄
ima.h
772 bytes
01/28/2018 09:20:33 PM
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📄
imc-pmu.h
2.87 KB
01/28/2018 09:20:33 PM
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📄
immap_cpm2.h
10.5 KB
01/28/2018 09:20:33 PM
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📄
io-defs.h
3.09 KB
01/28/2018 09:20:33 PM
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📄
io-workarounds.h
1.54 KB
01/28/2018 09:20:33 PM
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📄
io.h
28.02 KB
11/01/2022 04:52:05 PM
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📄
io_event_irq.h
1.91 KB
01/28/2018 09:20:33 PM
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📄
iommu.h
10.16 KB
01/28/2018 09:20:33 PM
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📄
ipic.h
3.51 KB
01/28/2018 09:20:33 PM
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📄
irq.h
1.83 KB
01/28/2018 09:20:33 PM
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📄
irq_work.h
252 bytes
11/01/2022 04:52:05 PM
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📄
irqflags.h
1.7 KB
01/28/2018 09:20:33 PM
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📄
isa-bridge.h
654 bytes
01/28/2018 09:20:33 PM
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📄
jump_label.h
1.62 KB
01/28/2018 09:20:33 PM
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📄
kdebug.h
291 bytes
01/28/2018 09:20:33 PM
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📄
kdump.h
1.37 KB
01/28/2018 09:20:33 PM
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📄
kexec.h
4.02 KB
11/01/2022 04:52:05 PM
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📄
keylargo.h
10.8 KB
01/28/2018 09:20:33 PM
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kgdb.h
2.06 KB
01/28/2018 09:20:33 PM
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📄
kmap_types.h
434 bytes
01/28/2018 09:20:33 PM
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kprobes.h
3.75 KB
01/28/2018 09:20:33 PM
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📄
kup.h
1021 bytes
11/01/2022 04:52:05 PM
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📄
kvm_asm.h
5.46 KB
11/01/2022 04:52:05 PM
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📄
kvm_book3s.h
12.06 KB
11/01/2022 04:52:05 PM
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📄
kvm_book3s_32.h
1.39 KB
01/28/2018 09:20:33 PM
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kvm_book3s_64.h
12.62 KB
11/01/2022 04:52:05 PM
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kvm_book3s_asm.h
4.4 KB
11/01/2022 04:52:05 PM
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kvm_booke.h
2.68 KB
01/28/2018 09:20:33 PM
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kvm_booke_hv_asm.h
2.03 KB
01/28/2018 09:20:33 PM
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kvm_fpu.h
2.74 KB
01/28/2018 09:20:33 PM
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kvm_host.h
19.92 KB
11/01/2022 04:52:05 PM
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kvm_para.h
1.49 KB
01/28/2018 09:20:33 PM
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kvm_ppc.h
34.83 KB
11/01/2022 04:52:05 PM
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📄
libata-portmap.h
249 bytes
01/28/2018 09:20:33 PM
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linkage.h
501 bytes
01/28/2018 09:20:33 PM
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livepatch.h
1.65 KB
01/28/2018 09:20:33 PM
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local.h
3.79 KB
01/28/2018 09:20:33 PM
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lppaca.h
5.02 KB
01/28/2018 09:20:33 PM
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lv1call.h
18.74 KB
01/28/2018 09:20:33 PM
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machdep.h
9.7 KB
11/01/2022 04:52:05 PM
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macio.h
3.89 KB
01/28/2018 09:20:33 PM
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mc146818rtc.h
943 bytes
01/28/2018 09:20:33 PM
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mce.h
5.58 KB
01/28/2018 09:20:33 PM
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mediabay.h
1.34 KB
01/28/2018 09:20:33 PM
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mm-arch-hooks.h
839 bytes
01/28/2018 09:20:33 PM
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mman.h
1.33 KB
01/28/2018 09:20:33 PM
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mmu-40x.h
1.94 KB
01/28/2018 09:20:33 PM
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mmu-44x.h
5.56 KB
01/28/2018 09:20:33 PM
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mmu-8xx.h
8.6 KB
11/01/2022 04:52:05 PM
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mmu-book3e.h
9.47 KB
01/28/2018 09:20:33 PM
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mmu.h
9.2 KB
01/28/2018 09:20:33 PM
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mmu_context.h
6.26 KB
11/01/2022 04:52:05 PM
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mmzone.h
1.08 KB
01/28/2018 09:20:33 PM
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module.h
2.47 KB
01/28/2018 09:20:33 PM
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mpc5121.h
3.82 KB
01/28/2018 09:20:33 PM
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mpc52xx.h
10.85 KB
01/28/2018 09:20:33 PM
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mpc52xx_psc.h
9.89 KB
01/28/2018 09:20:33 PM
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mpc5xxx.h
641 bytes
01/28/2018 09:20:33 PM
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mpc6xx.h
143 bytes
01/28/2018 09:20:33 PM
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mpc8260.h
742 bytes
01/28/2018 09:20:33 PM
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mpc85xx.h
2.52 KB
01/28/2018 09:20:33 PM
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mpic.h
13.97 KB
11/01/2022 04:52:05 PM
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mpic_msgr.h
3.52 KB
01/28/2018 09:20:33 PM
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mpic_timer.h
1.39 KB
01/28/2018 09:20:33 PM
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msi_bitmap.h
1.01 KB
01/28/2018 09:20:33 PM
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nmi.h
238 bytes
11/01/2022 04:52:05 PM
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nohash
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11/17/2022 06:42:21 AM
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nvram.h
3.21 KB
01/28/2018 09:20:33 PM
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ohare.h
1.64 KB
01/28/2018 09:20:33 PM
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opal-api.h
29.34 KB
11/01/2022 04:52:05 PM
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opal.h
16.53 KB
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oprofile_impl.h
3 KB
01/28/2018 09:20:33 PM
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paca.h
8.06 KB
11/01/2022 04:52:05 PM
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page.h
10.65 KB
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page_32.h
1.57 KB
01/28/2018 09:20:33 PM
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page_64.h
2.93 KB
11/01/2022 04:52:05 PM
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parport.h
956 bytes
01/28/2018 09:20:33 PM
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pasemi_dma.h
23.32 KB
01/28/2018 09:20:33 PM
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pci-bridge.h
9.21 KB
11/01/2022 04:52:05 PM
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pci.h
4.58 KB
11/01/2022 04:52:05 PM
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percpu.h
468 bytes
11/01/2022 04:52:05 PM
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perf_event.h
1.23 KB
01/28/2018 09:20:33 PM
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perf_event_fsl_emb.h
1.42 KB
01/28/2018 09:20:33 PM
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perf_event_server.h
6.3 KB
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pgalloc.h
620 bytes
01/28/2018 09:20:33 PM
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pgtable-be-types.h
2.76 KB
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pgtable-types.h
1.94 KB
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pgtable.h
2.45 KB
11/01/2022 04:52:05 PM
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plpar_wrappers.h
8.35 KB
01/28/2018 09:20:33 PM
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pmac_feature.h
13.08 KB
01/28/2018 09:20:33 PM
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pmac_low_i2c.h
3.24 KB
01/28/2018 09:20:33 PM
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pmac_pfunc.h
8.01 KB
01/28/2018 09:20:33 PM
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pmc.h
1.35 KB
01/28/2018 09:20:33 PM
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pmi.h
1.77 KB
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pnv-ocxl.h
1.4 KB
11/01/2022 04:52:05 PM
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pnv-pci.h
3.22 KB
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powernv.h
1.57 KB
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ppc-opcode.h
19.05 KB
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ppc-pci.h
2.69 KB
01/28/2018 09:20:33 PM
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ppc4xx.h
530 bytes
01/28/2018 09:20:33 PM
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ppc4xx_ocm.h
1.41 KB
01/28/2018 09:20:33 PM
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ppc_asm.h
21.63 KB
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probes.h
2.11 KB
01/28/2018 09:20:33 PM
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processor.h
15 KB
11/01/2022 04:52:05 PM
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prom.h
7.17 KB
01/28/2018 09:20:33 PM
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ps3.h
15.44 KB
11/01/2022 04:52:05 PM
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ps3av.h
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Editing: uninorth.h
Close
/* SPDX-License-Identifier: GPL-2.0 */ /* * uninorth.h: definitions for using the "UniNorth" host bridge chip * from Apple. This chip is used on "Core99" machines * This also includes U2 used on more recent MacRISC2/3 * machines and U3 (G5) * */ #ifdef __KERNEL__ #ifndef __ASM_UNINORTH_H__ #define __ASM_UNINORTH_H__ /* * Uni-N and U3 config space reg. definitions * * (Little endian) */ /* Address ranges selection. This one should work with Bandit too */ /* Not U3 */ #define UNI_N_ADDR_SELECT 0x48 #define UNI_N_ADDR_COARSE_MASK 0xffff0000 /* 256Mb regions at *0000000 */ #define UNI_N_ADDR_FINE_MASK 0x0000ffff /* 16Mb regions at f*000000 */ /* AGP registers */ /* Not U3 */ #define UNI_N_CFG_GART_BASE 0x8c #define UNI_N_CFG_AGP_BASE 0x90 #define UNI_N_CFG_GART_CTRL 0x94 #define UNI_N_CFG_INTERNAL_STATUS 0x98 #define UNI_N_CFG_GART_DUMMY_PAGE 0xa4 /* UNI_N_CFG_GART_CTRL bits definitions */ #define UNI_N_CFG_GART_INVAL 0x00000001 #define UNI_N_CFG_GART_ENABLE 0x00000100 #define UNI_N_CFG_GART_2xRESET 0x00010000 #define UNI_N_CFG_GART_DISSBADET 0x00020000 /* The following seems to only be used only on U3 <j.glisse@gmail.com> */ #define U3_N_CFG_GART_SYNCMODE 0x00040000 #define U3_N_CFG_GART_PERFRD 0x00080000 #define U3_N_CFG_GART_B2BGNT 0x00200000 #define U3_N_CFG_GART_FASTDDR 0x00400000 /* My understanding of UniNorth AGP as of UniNorth rev 1.0x, * revision 1.5 (x4 AGP) may need further changes. * * AGP_BASE register contains the base address of the AGP aperture on * the AGP bus. It doesn't seem to be visible to the CPU as of UniNorth 1.x, * even if decoding of this address range is enabled in the address select * register. Apparently, the only supported bases are 256Mb multiples * (high 4 bits of that register). * * GART_BASE register appear to contain the physical address of the GART * in system memory in the high address bits (page aligned), and the * GART size in the low order bits (number of GART pages) * * The GART format itself is one 32bits word per physical memory page. * This word contains, in little-endian format (!!!), the physical address * of the page in the high bits, and what appears to be an "enable" bit * in the LSB bit (0) that must be set to 1 when the entry is valid. * * Obviously, the GART is not cache coherent and so any change to it * must be flushed to memory (or maybe just make the GART space non * cachable). AGP memory itself doesn't seem to be cache coherent neither. * * In order to invalidate the GART (which is probably necessary to inval * the bridge internal TLBs), the following sequence has to be written, * in order, to the GART_CTRL register: * * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL * UNI_N_CFG_GART_ENABLE * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_2xRESET * UNI_N_CFG_GART_ENABLE * * As far as AGP "features" are concerned, it looks like fast write may * not be supported but this has to be confirmed. * * Turning on AGP seem to require a double invalidate operation, one before * setting the AGP command register, on after. * * Turning off AGP seems to require the following sequence: first wait * for the AGP to be idle by reading the internal status register, then * write in that order to the GART_CTRL register: * * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL * 0 * UNI_N_CFG_GART_2xRESET * 0 */ /* * Uni-N memory mapped reg. definitions * * Those registers are Big-Endian !! * * Their meaning come from either Darwin and/or from experiments I made with * the bootrom, I'm not sure about their exact meaning yet * */ /* Version of the UniNorth chip */ #define UNI_N_VERSION 0x0000 /* Known versions: 3,7 and 8 */ #define UNI_N_VERSION_107 0x0003 /* 1.0.7 */ #define UNI_N_VERSION_10A 0x0007 /* 1.0.10 */ #define UNI_N_VERSION_150 0x0011 /* 1.5 */ #define UNI_N_VERSION_200 0x0024 /* 2.0 */ #define UNI_N_VERSION_PANGEA 0x00C0 /* Integrated U1 + K */ #define UNI_N_VERSION_INTREPID 0x00D2 /* Integrated U2 + K */ #define UNI_N_VERSION_300 0x0030 /* 3.0 (U3 on G5) */ /* This register is used to enable/disable various clocks */ #define UNI_N_CLOCK_CNTL 0x0020 #define UNI_N_CLOCK_CNTL_PCI 0x00000001 /* PCI2 clock control */ #define UNI_N_CLOCK_CNTL_GMAC 0x00000002 /* GMAC clock control */ #define UNI_N_CLOCK_CNTL_FW 0x00000004 /* FireWire clock control */ #define UNI_N_CLOCK_CNTL_ATA100 0x00000010 /* ATA-100 clock control (U2) */ /* Power Management control */ #define UNI_N_POWER_MGT 0x0030 #define UNI_N_POWER_MGT_NORMAL 0x00 #define UNI_N_POWER_MGT_IDLE2 0x01 #define UNI_N_POWER_MGT_SLEEP 0x02 /* This register is configured by Darwin depending on the UniN * revision */ #define UNI_N_ARB_CTRL 0x0040 #define UNI_N_ARB_CTRL_QACK_DELAY_SHIFT 15 #define UNI_N_ARB_CTRL_QACK_DELAY_MASK 0x0e1f8000 #define UNI_N_ARB_CTRL_QACK_DELAY 0x30 #define UNI_N_ARB_CTRL_QACK_DELAY105 0x00 /* This one _might_ return the CPU number of the CPU reading it; * the bootROM decides whether to boot or to sleep/spinloop depending * on this register being 0 or not */ #define UNI_N_CPU_NUMBER 0x0050 /* This register appear to be read by the bootROM to decide what * to do on a non-recoverable reset (powerup or wakeup) */ #define UNI_N_HWINIT_STATE 0x0070 #define UNI_N_HWINIT_STATE_SLEEPING 0x01 #define UNI_N_HWINIT_STATE_RUNNING 0x02 /* This last bit appear to be used by the bootROM to know the second * CPU has started and will enter it's sleep loop with IP=0 */ #define UNI_N_HWINIT_STATE_CPU1_FLAG 0x10000000 /* This register controls AACK delay, which is set when 2004 iBook/PowerBook * is in low speed mode. */ #define UNI_N_AACK_DELAY 0x0100 #define UNI_N_AACK_DELAY_ENABLE 0x00000001 /* Clock status for Intrepid */ #define UNI_N_CLOCK_STOP_STATUS0 0x0150 #define UNI_N_CLOCK_STOPPED_EXTAGP 0x00200000 #define UNI_N_CLOCK_STOPPED_AGPDEL 0x00100000 #define UNI_N_CLOCK_STOPPED_I2S0_45_49 0x00080000 #define UNI_N_CLOCK_STOPPED_I2S0_18 0x00040000 #define UNI_N_CLOCK_STOPPED_I2S1_45_49 0x00020000 #define UNI_N_CLOCK_STOPPED_I2S1_18 0x00010000 #define UNI_N_CLOCK_STOPPED_TIMER 0x00008000 #define UNI_N_CLOCK_STOPPED_SCC_RTCLK18 0x00004000 #define UNI_N_CLOCK_STOPPED_SCC_RTCLK32 0x00002000 #define UNI_N_CLOCK_STOPPED_SCC_VIA32 0x00001000 #define UNI_N_CLOCK_STOPPED_SCC_SLOT0 0x00000800 #define UNI_N_CLOCK_STOPPED_SCC_SLOT1 0x00000400 #define UNI_N_CLOCK_STOPPED_SCC_SLOT2 0x00000200 #define UNI_N_CLOCK_STOPPED_PCI_FBCLKO 0x00000100 #define UNI_N_CLOCK_STOPPED_VEO0 0x00000080 #define UNI_N_CLOCK_STOPPED_VEO1 0x00000040 #define UNI_N_CLOCK_STOPPED_USB0 0x00000020 #define UNI_N_CLOCK_STOPPED_USB1 0x00000010 #define UNI_N_CLOCK_STOPPED_USB2 0x00000008 #define UNI_N_CLOCK_STOPPED_32 0x00000004 #define UNI_N_CLOCK_STOPPED_45 0x00000002 #define UNI_N_CLOCK_STOPPED_49 0x00000001 #define UNI_N_CLOCK_STOP_STATUS1 0x0160 #define UNI_N_CLOCK_STOPPED_PLL4REF 0x00080000 #define UNI_N_CLOCK_STOPPED_CPUDEL 0x00040000 #define UNI_N_CLOCK_STOPPED_CPU 0x00020000 #define UNI_N_CLOCK_STOPPED_BUF_REFCKO 0x00010000 #define UNI_N_CLOCK_STOPPED_PCI2 0x00008000 #define UNI_N_CLOCK_STOPPED_FW 0x00004000 #define UNI_N_CLOCK_STOPPED_GB 0x00002000 #define UNI_N_CLOCK_STOPPED_ATA66 0x00001000 #define UNI_N_CLOCK_STOPPED_ATA100 0x00000800 #define UNI_N_CLOCK_STOPPED_MAX 0x00000400 #define UNI_N_CLOCK_STOPPED_PCI1 0x00000200 #define UNI_N_CLOCK_STOPPED_KLPCI 0x00000100 #define UNI_N_CLOCK_STOPPED_USB0PCI 0x00000080 #define UNI_N_CLOCK_STOPPED_USB1PCI 0x00000040 #define UNI_N_CLOCK_STOPPED_USB2PCI 0x00000020 #define UNI_N_CLOCK_STOPPED_7PCI1 0x00000008 #define UNI_N_CLOCK_STOPPED_AGP 0x00000004 #define UNI_N_CLOCK_STOPPED_PCI0 0x00000002 #define UNI_N_CLOCK_STOPPED_18 0x00000001 /* Intrepid registe to OF do-platform-clockspreading */ #define UNI_N_CLOCK_SPREADING 0x190 /* Uninorth 1.5 rev. has additional perf. monitor registers at 0xf00-0xf50 */ /* * U3 specific registers */ /* U3 Toggle */ #define U3_TOGGLE_REG 0x00e0 #define U3_PMC_START_STOP 0x0001 #define U3_MPIC_RESET 0x0002 #define U3_MPIC_OUTPUT_ENABLE 0x0004 /* U3 API PHY Config 1 */ #define U3_API_PHY_CONFIG_1 0x23030 /* U3 HyperTransport registers */ #define U3_HT_CONFIG_BASE 0x70000 #define U3_HT_LINK_COMMAND 0x100 #define U3_HT_LINK_CONFIG 0x110 #define U3_HT_LINK_FREQ 0x120 #endif /* __ASM_UNINORTH_H__ */ #endif /* __KERNEL__ */