OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 8xx_immap.h	13.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 Kbuild	248 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 accounting.h	1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 agp.h	525 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 archrandom.h	1016 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 asm-compat.h	2.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	4.78 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 async_tx.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	13.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 backlight.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	3.57 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bitops.h	7.8 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 book3s	-	11/17/2022 06:42:21 AM	rwxr-xr-x
📄 bootx.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 btext.h	926 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	3.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	486 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	2.47 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cacheflush.h	3.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cell-pmu.h	4.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cell-regs.h	9.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	5.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	12.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 code-patching-asm.h	397 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 code-patching.h	5.01 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 compat.h	6.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 context_tracking.h	245 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 copro.h	769 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpm.h	5.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpm1.h	21.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpm2.h	48.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu_has_feature.h	1.31 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpufeature.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpuidle.h	3.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cputable.h	22.56 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cputhreads.h	2.92 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cputime.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	835 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dbdma.h	3.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dbell.h	2.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr-generic.h	1.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr-mmio.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr-native.h	4.42 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 dcr-regs.h	5.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr.h	2.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 debug.h	1.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 debugfs.h	489 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	3.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 device.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 disassemble.h	2.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	4.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	10.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dt_cpu_ftrs.h	816 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 edac.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 eeh.h	14.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 eeh_event.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ehv_pic.h	963 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	6.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 emergency-restart.h	43 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 emulated_ops.h	2.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 epapr_hcalls.h	16.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exception-64e.h	7.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exception-64s.h	22.72 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 exec.h	246 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable.h	904 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fadump.h	6.1 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 fb.h	483 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 feature-fixups.h	8.76 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 firmware.h	4.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	4.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fs_pd.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_85xx_cache_sram.h	1.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_gtm.h	1.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_hcalls.h	17.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_lbc.h	10.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_pamu_stash.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_pm.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 grackle.h	331 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 head-64.h	13.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 heathrow.h	2.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	2.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hmi.h	1.49 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hugetlb.h	4.73 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hvcall.h	15.35 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hvconsole.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hvcserver.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hvsi.h	2.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_breakpoint.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	5.24 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hydra.h	2.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i8259.h	361 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ibmebus.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 icswx.h	4.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	586 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ima.h	772 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 imc-pmu.h	2.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 immap_cpm2.h	10.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io-defs.h	3.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io-workarounds.h	1.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	28.02 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 io_event_irq.h	1.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 iommu.h	10.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ipic.h	3.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	1.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_work.h	252 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 irqflags.h	1.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 isa-bridge.h	654 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	1.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug.h	291 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdump.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	4.02 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 keylargo.h	10.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	2.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	434 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	3.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kup.h	1021 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_asm.h	5.46 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_book3s.h	12.06 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_book3s_32.h	1.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_book3s_64.h	12.62 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_book3s_asm.h	4.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_booke.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_booke_hv_asm.h	2.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_fpu.h	2.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_host.h	19.92 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_para.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_ppc.h	34.83 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 libata-portmap.h	249 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	501 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 livepatch.h	1.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 local.h	3.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 lppaca.h	5.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 lv1call.h	18.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 machdep.h	9.7 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 macio.h	3.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc.h	943 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mce.h	5.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mediabay.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mm-arch-hooks.h	839 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mman.h	1.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu-40x.h	1.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu-44x.h	5.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu-8xx.h	8.6 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mmu-book3e.h	9.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	9.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	6.26 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mmzone.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	2.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc5121.h	3.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc52xx.h	10.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc52xx_psc.h	9.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc5xxx.h	641 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc6xx.h	143 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc8260.h	742 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc85xx.h	2.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpic.h	13.97 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mpic_msgr.h	3.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpic_timer.h	1.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msi_bitmap.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nmi.h	238 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📁 nohash	-	11/17/2022 06:42:21 AM	rwxr-xr-x
📄 nvram.h	3.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ohare.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 opal-api.h	29.34 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 opal.h	16.53 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 oprofile_impl.h	3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 paca.h	8.06 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 page.h	10.65 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 page_32.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_64.h	2.93 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 parport.h	956 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pasemi_dma.h	23.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-bridge.h	9.21 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pci.h	4.58 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 percpu.h	468 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 perf_event.h	1.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event_fsl_emb.h	1.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event_server.h	6.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	620 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-be-types.h	2.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-types.h	1.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	2.45 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 plpar_wrappers.h	8.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmac_feature.h	13.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmac_low_i2c.h	3.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmac_pfunc.h	8.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmc.h	1.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmi.h	1.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pnv-ocxl.h	1.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pnv-pci.h	3.22 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 powernv.h	1.57 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ppc-opcode.h	19.05 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ppc-pci.h	2.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppc4xx.h	530 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppc4xx_ocm.h	1.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppc_asm.h	21.63 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 probes.h	2.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	15 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 prom.h	7.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ps3.h	15.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ps3av.h	23.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ps3gpu.h	2.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ps3stor.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pte-common.h	6.27 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pte-walk.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	7.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reg.h	61.61 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 reg_8xx.h	4.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reg_a2.h	6.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reg_booke.h	36.17 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 reg_fsl_emb.h	3.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rheap.h	2.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rio.h	637 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rtas.h	14.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 runlatch.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 scom.h	4.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seccomp.h	249 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	1.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 security_features.h	3.03 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 serial.h	677 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setjmp.h	630 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 setup.h	2.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 sfp-machine.h	12.38 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 shmparam.h	206 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	225 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 slice.h	1.12 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 smp.h	6.13 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 smu.h	19.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sparsemem.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	7.04 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 spinlock_types.h	424 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spu.h	25.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spu_csa.h	6.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spu_info.h	908 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spu_priv1.h	5.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sstep.h	4.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 swab.h	377 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 swiotlb.h	810 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	2.66 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 synch.h	1.36 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 syscall.h	2.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscalls.h	684 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 systbl.h	9.28 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tce.h	1.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 termios.h	860 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	5.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 time.h	4.82 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 timex.h	967 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 tlb.h	2.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	2.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tm.h	690 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	2.92 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 trace.h	4.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 trace_clock.h	517 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tsi108.h	3.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tsi108_irq.h	4.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tsi108_pci.h	1.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 types.h	1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	13.21 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 udbg.h	2.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uic.h	616 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	548 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uninorth.h	8.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	1.52 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 uprobes.h	1.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	2.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vas.h	4.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	1.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso_datapage.h	4.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 vga.h	1.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vio.h	4.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 word-at-a-time.h	4.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 xics.h	4.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 xilinx_intc.h	598 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 xilinx_pci.h	551 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 xive-regs.h	3.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 xive.h	5.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 xmon.h	927 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 xor.h	2.11 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: cpm1.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * MPC8xx Communication Processor Module.
 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
 *
 * This file contains structures and information for the communication
 * processor channels.  Some CPM control and status is available
 * through the MPC8xx internal memory map.  See immap.h for details.
 * This file only contains what I need for the moment, not the total
 * CPM capabilities.  I (or someone else) will add definitions as they
 * are needed.  -- Dan
 *
 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
 * bytes of the DP RAM and relocates the I2C parameter area to the
 * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
 * or other use.
 */
#ifndef __CPM1__
#define __CPM1__

#include <linux/init.h>
#include <asm/8xx_immap.h>
#include <asm/ptrace.h>
#include <asm/cpm.h>

/* CPM Command register.
*/
#define CPM_CR_RST	((ushort)0x8000)
#define CPM_CR_OPCODE	((ushort)0x0f00)
#define CPM_CR_CHAN	((ushort)0x00f0)
#define CPM_CR_FLG	((ushort)0x0001)

/* Channel numbers.
*/
#define CPM_CR_CH_SCC1		((ushort)0x0000)
#define CPM_CR_CH_I2C		((ushort)0x0001)	/* I2C and IDMA1 */
#define CPM_CR_CH_SCC2		((ushort)0x0004)
#define CPM_CR_CH_SPI		((ushort)0x0005)	/* SPI / IDMA2 / Timers */
#define CPM_CR_CH_TIMER		CPM_CR_CH_SPI
#define CPM_CR_CH_SCC3		((ushort)0x0008)
#define CPM_CR_CH_SMC1		((ushort)0x0009)	/* SMC1 / DSP1 */
#define CPM_CR_CH_SCC4		((ushort)0x000c)
#define CPM_CR_CH_SMC2		((ushort)0x000d)	/* SMC2 / DSP2 */

#define mk_cr_cmd(CH, CMD)	((CMD << 8) | (CH << 4))

/* Export the base address of the communication processor registers
 * and dual port ram.
 */
extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */

#define cpm_dpalloc cpm_muram_alloc
#define cpm_dpfree cpm_muram_free
#define cpm_dpram_addr cpm_muram_addr
#define cpm_dpram_phys cpm_muram_dma

extern void cpm_setbrg(uint brg, uint rate);

extern void __init cpm_load_patch(cpm8xx_t *cp);

extern void cpm_reset(void);

/* Parameter RAM offsets.
*/
#define PROFF_SCC1	((uint)0x0000)
#define PROFF_IIC	((uint)0x0080)
#define PROFF_SCC2	((uint)0x0100)
#define PROFF_SPI	((uint)0x0180)
#define PROFF_SCC3	((uint)0x0200)
#define PROFF_SMC1	((uint)0x0280)
#define PROFF_SCC4	((uint)0x0300)
#define PROFF_SMC2	((uint)0x0380)

/* Define enough so I can at least use the serial port as a UART.
 * The MBX uses SMC1 as the host serial port.
 */
typedef struct smc_uart {
	ushort	smc_rbase;	/* Rx Buffer descriptor base address */
	ushort	smc_tbase;	/* Tx Buffer descriptor base address */
	u_char	smc_rfcr;	/* Rx function code */
	u_char	smc_tfcr;	/* Tx function code */
	ushort	smc_mrblr;	/* Max receive buffer length */
	uint	smc_rstate;	/* Internal */
	uint	smc_idp;	/* Internal */
	ushort	smc_rbptr;	/* Internal */
	ushort	smc_ibc;	/* Internal */
	uint	smc_rxtmp;	/* Internal */
	uint	smc_tstate;	/* Internal */
	uint	smc_tdp;	/* Internal */
	ushort	smc_tbptr;	/* Internal */
	ushort	smc_tbc;	/* Internal */
	uint	smc_txtmp;	/* Internal */
	ushort	smc_maxidl;	/* Maximum idle characters */
	ushort	smc_tmpidl;	/* Temporary idle counter */
	ushort	smc_brklen;	/* Last received break length */
	ushort	smc_brkec;	/* rcv'd break condition counter */
	ushort	smc_brkcr;	/* xmt break count register */
	ushort	smc_rmask;	/* Temporary bit mask */
	char	res1[8];	/* Reserved */
	ushort	smc_rpbase;	/* Relocation pointer */
} smc_uart_t;

/* Function code bits.
*/
#define SMC_EB	((u_char)0x10)	/* Set big endian byte order */

/* SMC uart mode register.
*/
#define	SMCMR_REN	((ushort)0x0001)
#define SMCMR_TEN	((ushort)0x0002)
#define SMCMR_DM	((ushort)0x000c)
#define SMCMR_SM_GCI	((ushort)0x0000)
#define SMCMR_SM_UART	((ushort)0x0020)
#define SMCMR_SM_TRANS	((ushort)0x0030)
#define SMCMR_SM_MASK	((ushort)0x0030)
#define SMCMR_PM_EVEN	((ushort)0x0100)	/* Even parity, else odd */
#define SMCMR_REVD	SMCMR_PM_EVEN
#define SMCMR_PEN	((ushort)0x0200)	/* Parity enable */
#define SMCMR_BS	SMCMR_PEN
#define SMCMR_SL	((ushort)0x0400)	/* Two stops, else one */
#define SMCR_CLEN_MASK	((ushort)0x7800)	/* Character length */
#define smcr_mk_clen(C)	(((C) << 11) & SMCR_CLEN_MASK)

/* SMC2 as Centronics parallel printer.  It is half duplex, in that
 * it can only receive or transmit.  The parameter ram values for
 * each direction are either unique or properly overlap, so we can
 * include them in one structure.
 */
typedef struct smc_centronics {
	ushort	scent_rbase;
	ushort	scent_tbase;
	u_char	scent_cfcr;
	u_char	scent_smask;
	ushort	scent_mrblr;
	uint	scent_rstate;
	uint	scent_r_ptr;
	ushort	scent_rbptr;
	ushort	scent_r_cnt;
	uint	scent_rtemp;
	uint	scent_tstate;
	uint	scent_t_ptr;
	ushort	scent_tbptr;
	ushort	scent_t_cnt;
	uint	scent_ttemp;
	ushort	scent_max_sl;
	ushort	scent_sl_cnt;
	ushort	scent_character1;
	ushort	scent_character2;
	ushort	scent_character3;
	ushort	scent_character4;
	ushort	scent_character5;
	ushort	scent_character6;
	ushort	scent_character7;
	ushort	scent_character8;
	ushort	scent_rccm;
	ushort	scent_rccr;
} smc_cent_t;

/* Centronics Status Mask Register.
*/
#define SMC_CENT_F	((u_char)0x08)
#define SMC_CENT_PE	((u_char)0x04)
#define SMC_CENT_S	((u_char)0x02)

/* SMC Event and Mask register.
*/
#define	SMCM_BRKE	((unsigned char)0x40)	/* When in UART Mode */
#define	SMCM_BRK	((unsigned char)0x10)	/* When in UART Mode */
#define	SMCM_TXE	((unsigned char)0x10)	/* When in Transparent Mode */
#define	SMCM_BSY	((unsigned char)0x04)
#define	SMCM_TX		((unsigned char)0x02)
#define	SMCM_RX		((unsigned char)0x01)

/* Baud rate generators.
*/
#define CPM_BRG_RST		((uint)0x00020000)
#define CPM_BRG_EN		((uint)0x00010000)
#define CPM_BRG_EXTC_INT	((uint)0x00000000)
#define CPM_BRG_EXTC_CLK2	((uint)0x00004000)
#define CPM_BRG_EXTC_CLK6	((uint)0x00008000)
#define CPM_BRG_ATB		((uint)0x00002000)
#define CPM_BRG_CD_MASK		((uint)0x00001ffe)
#define CPM_BRG_DIV16		((uint)0x00000001)

/* SI Clock Route Register
*/
#define SICR_RCLK_SCC1_BRG1	((uint)0x00000000)
#define SICR_TCLK_SCC1_BRG1	((uint)0x00000000)
#define SICR_RCLK_SCC2_BRG2	((uint)0x00000800)
#define SICR_TCLK_SCC2_BRG2	((uint)0x00000100)
#define SICR_RCLK_SCC3_BRG3	((uint)0x00100000)
#define SICR_TCLK_SCC3_BRG3	((uint)0x00020000)
#define SICR_RCLK_SCC4_BRG4	((uint)0x18000000)
#define SICR_TCLK_SCC4_BRG4	((uint)0x03000000)

/* SCCs.
*/
#define SCC_GSMRH_IRP		((uint)0x00040000)
#define SCC_GSMRH_GDE		((uint)0x00010000)
#define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
#define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
#define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
#define SCC_GSMRH_REVD		((uint)0x00002000)
#define SCC_GSMRH_TRX		((uint)0x00001000)
#define SCC_GSMRH_TTX		((uint)0x00000800)
#define SCC_GSMRH_CDP		((uint)0x00000400)
#define SCC_GSMRH_CTSP		((uint)0x00000200)
#define SCC_GSMRH_CDS		((uint)0x00000100)
#define SCC_GSMRH_CTSS		((uint)0x00000080)
#define SCC_GSMRH_TFL		((uint)0x00000040)
#define SCC_GSMRH_RFW		((uint)0x00000020)
#define SCC_GSMRH_TXSY		((uint)0x00000010)
#define SCC_GSMRH_SYNL16	((uint)0x0000000c)
#define SCC_GSMRH_SYNL8		((uint)0x00000008)
#define SCC_GSMRH_SYNL4		((uint)0x00000004)
#define SCC_GSMRH_RTSM		((uint)0x00000002)
#define SCC_GSMRH_RSYN		((uint)0x00000001)

#define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
#define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
#define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
#define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
#define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
#define SCC_GSMRL_TCI		((uint)0x10000000)
#define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
#define SCC_GSMRL_TSNC_4	((uint)0x08000000)
#define SCC_GSMRL_TSNC_14	((uint)0x04000000)
#define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
#define SCC_GSMRL_RINV		((uint)0x02000000)
#define SCC_GSMRL_TINV		((uint)0x01000000)
#define SCC_GSMRL_TPL_128	((uint)0x00c00000)
#define SCC_GSMRL_TPL_64	((uint)0x00a00000)
#define SCC_GSMRL_TPL_48	((uint)0x00800000)
#define SCC_GSMRL_TPL_32	((uint)0x00600000)
#define SCC_GSMRL_TPL_16	((uint)0x00400000)
#define SCC_GSMRL_TPL_8		((uint)0x00200000)
#define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
#define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
#define SCC_GSMRL_TPP_01	((uint)0x00100000)
#define SCC_GSMRL_TPP_10	((uint)0x00080000)
#define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
#define SCC_GSMRL_TEND		((uint)0x00040000)
#define SCC_GSMRL_TDCR_32	((uint)0x00030000)
#define SCC_GSMRL_TDCR_16	((uint)0x00020000)
#define SCC_GSMRL_TDCR_8	((uint)0x00010000)
#define SCC_GSMRL_TDCR_1	((uint)0x00000000)
#define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
#define SCC_GSMRL_RDCR_16	((uint)0x00008000)
#define SCC_GSMRL_RDCR_8	((uint)0x00004000)
#define SCC_GSMRL_RDCR_1	((uint)0x00000000)
#define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
#define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
#define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
#define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
#define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
#define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
#define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
#define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
#define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
#define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
#define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
#define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
#define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
#define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
#define SCC_GSMRL_ENR		((uint)0x00000020)
#define SCC_GSMRL_ENT		((uint)0x00000010)
#define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
#define SCC_GSMRL_MODE_QMC	((uint)0x0000000a)
#define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
#define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
#define SCC_GSMRL_MODE_V14	((uint)0x00000007)
#define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
#define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
#define SCC_GSMRL_MODE_UART	((uint)0x00000004)
#define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
#define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
#define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)

#define SCC_TODR_TOD		((ushort)0x8000)

/* SCC Event and Mask register.
*/
#define	SCCM_TXE	((unsigned char)0x10)
#define	SCCM_BSY	((unsigned char)0x04)
#define	SCCM_TX		((unsigned char)0x02)
#define	SCCM_RX		((unsigned char)0x01)

typedef struct scc_param {
	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
	u_char	scc_rfcr;	/* Rx function code */
	u_char	scc_tfcr;	/* Tx function code */
	ushort	scc_mrblr;	/* Max receive buffer length */
	uint	scc_rstate;	/* Internal */
	uint	scc_idp;	/* Internal */
	ushort	scc_rbptr;	/* Internal */
	ushort	scc_ibc;	/* Internal */
	uint	scc_rxtmp;	/* Internal */
	uint	scc_tstate;	/* Internal */
	uint	scc_tdp;	/* Internal */
	ushort	scc_tbptr;	/* Internal */
	ushort	scc_tbc;	/* Internal */
	uint	scc_txtmp;	/* Internal */
	uint	scc_rcrc;	/* Internal */
	uint	scc_tcrc;	/* Internal */
} sccp_t;

/* Function code bits.
*/
#define SCC_EB	((u_char)0x10)	/* Set big endian byte order */

/* CPM Ethernet through SCCx.
 */
typedef struct scc_enet {
	sccp_t	sen_genscc;
	uint	sen_cpres;	/* Preset CRC */
	uint	sen_cmask;	/* Constant mask for CRC */
	uint	sen_crcec;	/* CRC Error counter */
	uint	sen_alec;	/* alignment error counter */
	uint	sen_disfc;	/* discard frame counter */
	ushort	sen_pads;	/* Tx short frame pad character */
	ushort	sen_retlim;	/* Retry limit threshold */
	ushort	sen_retcnt;	/* Retry limit counter */
	ushort	sen_maxflr;	/* maximum frame length register */
	ushort	sen_minflr;	/* minimum frame length register */
	ushort	sen_maxd1;	/* maximum DMA1 length */
	ushort	sen_maxd2;	/* maximum DMA2 length */
	ushort	sen_maxd;	/* Rx max DMA */
	ushort	sen_dmacnt;	/* Rx DMA counter */
	ushort	sen_maxb;	/* Max BD byte count */
	ushort	sen_gaddr1;	/* Group address filter */
	ushort	sen_gaddr2;
	ushort	sen_gaddr3;
	ushort	sen_gaddr4;
	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
	uint	sen_tbuf0rba;	/* Internal */
	uint	sen_tbuf0crc;	/* Internal */
	ushort	sen_tbuf0bcnt;	/* Internal */
	ushort	sen_paddrh;	/* physical address (MSB) */
	ushort	sen_paddrm;
	ushort	sen_paddrl;	/* physical address (LSB) */
	ushort	sen_pper;	/* persistence */
	ushort	sen_rfbdptr;	/* Rx first BD pointer */
	ushort	sen_tfbdptr;	/* Tx first BD pointer */
	ushort	sen_tlbdptr;	/* Tx last BD pointer */
	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
	uint	sen_tbuf1rba;	/* Internal */
	uint	sen_tbuf1crc;	/* Internal */
	ushort	sen_tbuf1bcnt;	/* Internal */
	ushort	sen_txlen;	/* Tx Frame length counter */
	ushort	sen_iaddr1;	/* Individual address filter */
	ushort	sen_iaddr2;
	ushort	sen_iaddr3;
	ushort	sen_iaddr4;
	ushort	sen_boffcnt;	/* Backoff counter */

/* NOTE: Some versions of the manual have the following items
	 * incorrectly documented.  Below is the proper order.
	 */
	ushort	sen_taddrh;	/* temp address (MSB) */
	ushort	sen_taddrm;
	ushort	sen_taddrl;	/* temp address (LSB) */
} scc_enet_t;

/* SCC Event register as used by Ethernet.
*/
#define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
#define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
#define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
#define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
#define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
#define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */

/* SCC Mode Register (PMSR) as used by Ethernet.
*/
#define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
#define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
#define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
#define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
#define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
#define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
#define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
#define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
#define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
#define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
#define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
#define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
#define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */

/* SCC as UART
*/
typedef struct scc_uart {
	sccp_t	scc_genscc;
	char	res1[8];	/* Reserved */
	ushort	scc_maxidl;	/* Maximum idle chars */
	ushort	scc_idlc;	/* temp idle counter */
	ushort	scc_brkcr;	/* Break count register */
	ushort	scc_parec;	/* receive parity error counter */
	ushort	scc_frmec;	/* receive framing error counter */
	ushort	scc_nosec;	/* receive noise counter */
	ushort	scc_brkec;	/* receive break condition counter */
	ushort	scc_brkln;	/* last received break length */
	ushort	scc_uaddr1;	/* UART address character 1 */
	ushort	scc_uaddr2;	/* UART address character 2 */
	ushort	scc_rtemp;	/* Temp storage */
	ushort	scc_toseq;	/* Transmit out of sequence char */
	ushort	scc_char1;	/* control character 1 */
	ushort	scc_char2;	/* control character 2 */
	ushort	scc_char3;	/* control character 3 */
	ushort	scc_char4;	/* control character 4 */
	ushort	scc_char5;	/* control character 5 */
	ushort	scc_char6;	/* control character 6 */
	ushort	scc_char7;	/* control character 7 */
	ushort	scc_char8;	/* control character 8 */
	ushort	scc_rccm;	/* receive control character mask */
	ushort	scc_rccr;	/* receive control character register */
	ushort	scc_rlbc;	/* receive last break character */
} scc_uart_t;

/* SCC Event and Mask registers when it is used as a UART.
*/
#define UART_SCCM_GLR		((ushort)0x1000)
#define UART_SCCM_GLT		((ushort)0x0800)
#define UART_SCCM_AB		((ushort)0x0200)
#define UART_SCCM_IDL		((ushort)0x0100)
#define UART_SCCM_GRA		((ushort)0x0080)
#define UART_SCCM_BRKE		((ushort)0x0040)
#define UART_SCCM_BRKS		((ushort)0x0020)
#define UART_SCCM_CCR		((ushort)0x0008)
#define UART_SCCM_BSY		((ushort)0x0004)
#define UART_SCCM_TX		((ushort)0x0002)
#define UART_SCCM_RX		((ushort)0x0001)

/* The SCC PMSR when used as a UART.
*/
#define SCU_PSMR_FLC		((ushort)0x8000)
#define SCU_PSMR_SL		((ushort)0x4000)
#define SCU_PSMR_CL		((ushort)0x3000)
#define SCU_PSMR_UM		((ushort)0x0c00)
#define SCU_PSMR_FRZ		((ushort)0x0200)
#define SCU_PSMR_RZS		((ushort)0x0100)
#define SCU_PSMR_SYN		((ushort)0x0080)
#define SCU_PSMR_DRT		((ushort)0x0040)
#define SCU_PSMR_PEN		((ushort)0x0010)
#define SCU_PSMR_RPM		((ushort)0x000c)
#define SCU_PSMR_REVP		((ushort)0x0008)
#define SCU_PSMR_TPM		((ushort)0x0003)
#define SCU_PSMR_TEVP		((ushort)0x0002)

/* CPM Transparent mode SCC.
 */
typedef struct scc_trans {
	sccp_t	st_genscc;
	uint	st_cpres;	/* Preset CRC */
	uint	st_cmask;	/* Constant mask for CRC */
} scc_trans_t;

/* IIC parameter RAM.
*/
typedef struct iic {
	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
	u_char	iic_rfcr;	/* Rx function code */
	u_char	iic_tfcr;	/* Tx function code */
	ushort	iic_mrblr;	/* Max receive buffer length */
	uint	iic_rstate;	/* Internal */
	uint	iic_rdp;	/* Internal */
	ushort	iic_rbptr;	/* Internal */
	ushort	iic_rbc;	/* Internal */
	uint	iic_rxtmp;	/* Internal */
	uint	iic_tstate;	/* Internal */
	uint	iic_tdp;	/* Internal */
	ushort	iic_tbptr;	/* Internal */
	ushort	iic_tbc;	/* Internal */
	uint	iic_txtmp;	/* Internal */
	char	res1[4];	/* Reserved */
	ushort	iic_rpbase;	/* Relocation pointer */
	char	res2[2];	/* Reserved */
} iic_t;

/*
 * RISC Controller Configuration Register definitons
 */
#define RCCR_TIME	0x8000			/* RISC Timer Enable */
#define RCCR_TIMEP(t)	(((t) & 0x3F)<<8)	/* RISC Timer Period */
#define RCCR_TIME_MASK	0x00FF			/* not RISC Timer related bits */

/* RISC Timer Parameter RAM offset */
#define PROFF_RTMR	((uint)0x01B0)

typedef struct risc_timer_pram {
	unsigned short	tm_base;	/* RISC Timer Table Base Address */
	unsigned short	tm_ptr;		/* RISC Timer Table Pointer (internal) */
	unsigned short	r_tmr;		/* RISC Timer Mode Register */
	unsigned short	r_tmv;		/* RISC Timer Valid Register */
	unsigned long	tm_cmd;		/* RISC Timer Command Register */
	unsigned long	tm_cnt;		/* RISC Timer Internal Count */
} rt_pram_t;

/* Bits in RISC Timer Command Register */
#define TM_CMD_VALID	0x80000000	/* Valid - Enables the timer */
#define TM_CMD_RESTART	0x40000000	/* Restart - for automatic restart */
#define TM_CMD_PWM	0x20000000	/* Run in Pulse Width Modulation Mode */
#define TM_CMD_NUM(n)	(((n)&0xF)<<16)	/* Timer Number */
#define TM_CMD_PERIOD(p) ((p)&0xFFFF)	/* Timer Period */

/* CPM interrupts.  There are nearly 32 interrupts generated by CPM
 * channels or devices.  All of these are presented to the PPC core
 * as a single interrupt.  The CPM interrupt handler dispatches its
 * own handlers, in a similar fashion to the PPC core handler.  We
 * use the table as defined in the manuals (i.e. no special high
 * priority and SCC1 == SCCa, etc...).
 */
#define CPMVEC_NR		32
#define	CPMVEC_PIO_PC15		((ushort)0x1f)
#define	CPMVEC_SCC1		((ushort)0x1e)
#define	CPMVEC_SCC2		((ushort)0x1d)
#define	CPMVEC_SCC3		((ushort)0x1c)
#define	CPMVEC_SCC4		((ushort)0x1b)
#define	CPMVEC_PIO_PC14		((ushort)0x1a)
#define	CPMVEC_TIMER1		((ushort)0x19)
#define	CPMVEC_PIO_PC13		((ushort)0x18)
#define	CPMVEC_PIO_PC12		((ushort)0x17)
#define	CPMVEC_SDMA_CB_ERR	((ushort)0x16)
#define CPMVEC_IDMA1		((ushort)0x15)
#define CPMVEC_IDMA2		((ushort)0x14)
#define CPMVEC_TIMER2		((ushort)0x12)
#define CPMVEC_RISCTIMER	((ushort)0x11)
#define CPMVEC_I2C		((ushort)0x10)
#define	CPMVEC_PIO_PC11		((ushort)0x0f)
#define	CPMVEC_PIO_PC10		((ushort)0x0e)
#define CPMVEC_TIMER3		((ushort)0x0c)
#define	CPMVEC_PIO_PC9		((ushort)0x0b)
#define	CPMVEC_PIO_PC8		((ushort)0x0a)
#define	CPMVEC_PIO_PC7		((ushort)0x09)
#define CPMVEC_TIMER4		((ushort)0x07)
#define	CPMVEC_PIO_PC6		((ushort)0x06)
#define	CPMVEC_SPI		((ushort)0x05)
#define	CPMVEC_SMC1		((ushort)0x04)
#define	CPMVEC_SMC2		((ushort)0x03)
#define	CPMVEC_PIO_PC5		((ushort)0x02)
#define	CPMVEC_PIO_PC4		((ushort)0x01)
#define	CPMVEC_ERROR		((ushort)0x00)

/* CPM interrupt configuration vector.
*/
#define	CICR_SCD_SCC4		((uint)0x00c00000)	/* SCC4 @ SCCd */
#define	CICR_SCC_SCC3		((uint)0x00200000)	/* SCC3 @ SCCc */
#define	CICR_SCB_SCC2		((uint)0x00040000)	/* SCC2 @ SCCb */
#define	CICR_SCA_SCC1		((uint)0x00000000)	/* SCC1 @ SCCa */
#define CICR_IRL_MASK		((uint)0x0000e000)	/* Core interrupt */
#define CICR_HP_MASK		((uint)0x00001f00)	/* Hi-pri int. */
#define CICR_IEN		((uint)0x00000080)	/* Int. enable */
#define CICR_SPS		((uint)0x00000001)	/* SCC Spread */

#define CPM_PIN_INPUT     0
#define CPM_PIN_OUTPUT    1
#define CPM_PIN_PRIMARY   0
#define CPM_PIN_SECONDARY 2
#define CPM_PIN_GPIO      4
#define CPM_PIN_OPENDRAIN 8
#define CPM_PIN_FALLEDGE  16
#define CPM_PIN_ANYEDGE   0

enum cpm_port {
	CPM_PORTA,
	CPM_PORTB,
	CPM_PORTC,
	CPM_PORTD,
	CPM_PORTE,
};

void cpm1_set_pin(enum cpm_port port, int pin, int flags);

enum cpm_clk_dir {
	CPM_CLK_RX,
	CPM_CLK_TX,
	CPM_CLK_RTX
};

enum cpm_clk_target {
	CPM_CLK_SCC1,
	CPM_CLK_SCC2,
	CPM_CLK_SCC3,
	CPM_CLK_SCC4,
	CPM_CLK_SMC1,
	CPM_CLK_SMC2,
};

enum cpm_clk {
	CPM_BRG1,	/* Baud Rate Generator  1 */
	CPM_BRG2,	/* Baud Rate Generator  2 */
	CPM_BRG3,	/* Baud Rate Generator  3 */
	CPM_BRG4,	/* Baud Rate Generator  4 */
	CPM_CLK1,	/* Clock  1 */
	CPM_CLK2,	/* Clock  2 */
	CPM_CLK3,	/* Clock  3 */
	CPM_CLK4,	/* Clock  4 */
	CPM_CLK5,	/* Clock  5 */
	CPM_CLK6,	/* Clock  6 */
	CPM_CLK7,	/* Clock  7 */
	CPM_CLK8,	/* Clock  8 */
};

int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode);

#endif /* __CPM1__ */