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linux-headers-4.15.0-197
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powerpc
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include
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asm
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Size
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11/17/2022 06:42:16 AM
rwxr-xr-x
📄
8xx_immap.h
13.77 KB
01/28/2018 09:20:33 PM
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📄
Kbuild
248 bytes
01/28/2018 09:20:33 PM
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accounting.h
1 KB
01/28/2018 09:20:33 PM
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agp.h
525 bytes
01/28/2018 09:20:33 PM
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archrandom.h
1016 bytes
11/01/2022 04:52:05 PM
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asm-compat.h
2.53 KB
01/28/2018 09:20:33 PM
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asm-offsets.h
35 bytes
01/28/2018 09:20:33 PM
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asm-prototypes.h
4.78 KB
11/01/2022 04:52:05 PM
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async_tx.h
1.64 KB
01/28/2018 09:20:33 PM
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atomic.h
13.57 KB
01/28/2018 09:20:33 PM
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backlight.h
1.09 KB
01/28/2018 09:20:33 PM
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barrier.h
3.57 KB
11/01/2022 04:52:05 PM
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bitops.h
7.8 KB
11/01/2022 04:52:05 PM
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book3s
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11/17/2022 06:42:21 AM
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bootx.h
1.12 KB
01/28/2018 09:20:33 PM
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btext.h
926 bytes
01/28/2018 09:20:33 PM
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bug.h
3.55 KB
01/28/2018 09:20:33 PM
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bugs.h
486 bytes
01/28/2018 09:20:33 PM
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cache.h
2.47 KB
11/01/2022 04:52:05 PM
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cacheflush.h
3.76 KB
01/28/2018 09:20:33 PM
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cell-pmu.h
4.04 KB
01/28/2018 09:20:33 PM
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cell-regs.h
9.57 KB
01/28/2018 09:20:33 PM
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checksum.h
5.85 KB
01/28/2018 09:20:33 PM
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cmpxchg.h
12.16 KB
01/28/2018 09:20:33 PM
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📄
code-patching-asm.h
397 bytes
11/01/2022 04:52:05 PM
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code-patching.h
5.01 KB
11/01/2022 04:52:05 PM
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compat.h
6.26 KB
01/28/2018 09:20:33 PM
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context_tracking.h
245 bytes
01/28/2018 09:20:33 PM
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copro.h
769 bytes
01/28/2018 09:20:33 PM
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cpm.h
5.09 KB
01/28/2018 09:20:33 PM
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cpm1.h
21.08 KB
01/28/2018 09:20:33 PM
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cpm2.h
48.43 KB
01/28/2018 09:20:33 PM
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cpu_has_feature.h
1.31 KB
11/01/2022 04:52:05 PM
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cpufeature.h
1.18 KB
01/28/2018 09:20:33 PM
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cpuidle.h
3.31 KB
01/28/2018 09:20:33 PM
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cputable.h
22.56 KB
11/01/2022 04:52:05 PM
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cputhreads.h
2.92 KB
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cputime.h
1.59 KB
01/28/2018 09:20:33 PM
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current.h
835 bytes
01/28/2018 09:20:33 PM
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dbdma.h
3.72 KB
01/28/2018 09:20:33 PM
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dbell.h
2.78 KB
01/28/2018 09:20:33 PM
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dcr-generic.h
1.58 KB
01/28/2018 09:20:33 PM
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dcr-mmio.h
1.68 KB
01/28/2018 09:20:33 PM
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dcr-native.h
4.42 KB
11/01/2022 04:52:05 PM
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dcr-regs.h
5.71 KB
01/28/2018 09:20:33 PM
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dcr.h
2.73 KB
01/28/2018 09:20:33 PM
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debug.h
1.97 KB
01/28/2018 09:20:33 PM
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debugfs.h
489 bytes
01/28/2018 09:20:33 PM
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delay.h
3.42 KB
01/28/2018 09:20:33 PM
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device.h
1.1 KB
01/28/2018 09:20:33 PM
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disassemble.h
2.73 KB
01/28/2018 09:20:33 PM
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dma-mapping.h
4.12 KB
01/28/2018 09:20:33 PM
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dma.h
10.51 KB
01/28/2018 09:20:33 PM
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dt_cpu_ftrs.h
816 bytes
01/28/2018 09:20:33 PM
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edac.h
1.08 KB
01/28/2018 09:20:33 PM
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eeh.h
14.44 KB
01/28/2018 09:20:33 PM
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eeh_event.h
1.36 KB
01/28/2018 09:20:33 PM
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ehv_pic.h
963 bytes
01/28/2018 09:20:33 PM
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elf.h
6.29 KB
01/28/2018 09:20:33 PM
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emergency-restart.h
43 bytes
01/28/2018 09:20:33 PM
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emulated_ops.h
2.58 KB
01/28/2018 09:20:33 PM
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epapr_hcalls.h
16.44 KB
01/28/2018 09:20:33 PM
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exception-64e.h
7.21 KB
01/28/2018 09:20:33 PM
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exception-64s.h
22.72 KB
11/01/2022 04:52:05 PM
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exec.h
246 bytes
01/28/2018 09:20:33 PM
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extable.h
904 bytes
01/28/2018 09:20:33 PM
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fadump.h
6.1 KB
11/01/2022 04:52:05 PM
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fb.h
483 bytes
01/28/2018 09:20:33 PM
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📄
feature-fixups.h
8.76 KB
11/01/2022 04:52:05 PM
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📄
firmware.h
4.71 KB
01/28/2018 09:20:33 PM
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📄
fixmap.h
2.33 KB
01/28/2018 09:20:33 PM
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📄
floppy.h
4.86 KB
01/28/2018 09:20:33 PM
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📄
fs_pd.h
1.02 KB
01/28/2018 09:20:33 PM
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📄
fsl_85xx_cache_sram.h
1.43 KB
01/28/2018 09:20:33 PM
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📄
fsl_gtm.h
1.38 KB
01/28/2018 09:20:33 PM
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📄
fsl_hcalls.h
17.2 KB
01/28/2018 09:20:33 PM
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📄
fsl_lbc.h
10.9 KB
01/28/2018 09:20:33 PM
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fsl_pamu_stash.h
1.1 KB
01/28/2018 09:20:33 PM
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📄
fsl_pm.h
1.36 KB
01/28/2018 09:20:33 PM
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📄
ftrace.h
2.1 KB
01/28/2018 09:20:33 PM
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📄
futex.h
2.4 KB
11/01/2022 04:52:05 PM
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grackle.h
331 bytes
01/28/2018 09:20:33 PM
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hardirq.h
1.15 KB
01/28/2018 09:20:33 PM
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head-64.h
13.86 KB
01/28/2018 09:20:33 PM
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heathrow.h
2.53 KB
01/28/2018 09:20:33 PM
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highmem.h
2.41 KB
01/28/2018 09:20:33 PM
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📄
hmi.h
1.49 KB
11/01/2022 04:52:05 PM
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📄
hugetlb.h
4.73 KB
11/01/2022 04:52:05 PM
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hvcall.h
15.35 KB
11/01/2022 04:52:05 PM
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📄
hvconsole.h
1.37 KB
01/28/2018 09:20:33 PM
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hvcserver.h
2.09 KB
01/28/2018 09:20:33 PM
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📄
hvsi.h
2.78 KB
01/28/2018 09:20:33 PM
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hw_breakpoint.h
3.07 KB
01/28/2018 09:20:33 PM
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hw_irq.h
5.24 KB
11/01/2022 04:52:05 PM
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📄
hydra.h
2.91 KB
01/28/2018 09:20:33 PM
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📄
i8259.h
361 bytes
01/28/2018 09:20:33 PM
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📄
ibmebus.h
2.15 KB
01/28/2018 09:20:33 PM
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📄
icswx.h
4.71 KB
01/28/2018 09:20:33 PM
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📄
ide.h
586 bytes
01/28/2018 09:20:33 PM
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📄
ima.h
772 bytes
01/28/2018 09:20:33 PM
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📄
imc-pmu.h
2.87 KB
01/28/2018 09:20:33 PM
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📄
immap_cpm2.h
10.5 KB
01/28/2018 09:20:33 PM
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📄
io-defs.h
3.09 KB
01/28/2018 09:20:33 PM
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📄
io-workarounds.h
1.54 KB
01/28/2018 09:20:33 PM
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📄
io.h
28.02 KB
11/01/2022 04:52:05 PM
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📄
io_event_irq.h
1.91 KB
01/28/2018 09:20:33 PM
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📄
iommu.h
10.16 KB
01/28/2018 09:20:33 PM
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📄
ipic.h
3.51 KB
01/28/2018 09:20:33 PM
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📄
irq.h
1.83 KB
01/28/2018 09:20:33 PM
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📄
irq_work.h
252 bytes
11/01/2022 04:52:05 PM
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📄
irqflags.h
1.7 KB
01/28/2018 09:20:33 PM
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📄
isa-bridge.h
654 bytes
01/28/2018 09:20:33 PM
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📄
jump_label.h
1.62 KB
01/28/2018 09:20:33 PM
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📄
kdebug.h
291 bytes
01/28/2018 09:20:33 PM
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📄
kdump.h
1.37 KB
01/28/2018 09:20:33 PM
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📄
kexec.h
4.02 KB
11/01/2022 04:52:05 PM
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📄
keylargo.h
10.8 KB
01/28/2018 09:20:33 PM
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kgdb.h
2.06 KB
01/28/2018 09:20:33 PM
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📄
kmap_types.h
434 bytes
01/28/2018 09:20:33 PM
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kprobes.h
3.75 KB
01/28/2018 09:20:33 PM
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📄
kup.h
1021 bytes
11/01/2022 04:52:05 PM
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📄
kvm_asm.h
5.46 KB
11/01/2022 04:52:05 PM
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📄
kvm_book3s.h
12.06 KB
11/01/2022 04:52:05 PM
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📄
kvm_book3s_32.h
1.39 KB
01/28/2018 09:20:33 PM
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kvm_book3s_64.h
12.62 KB
11/01/2022 04:52:05 PM
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kvm_book3s_asm.h
4.4 KB
11/01/2022 04:52:05 PM
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kvm_booke.h
2.68 KB
01/28/2018 09:20:33 PM
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kvm_booke_hv_asm.h
2.03 KB
01/28/2018 09:20:33 PM
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kvm_fpu.h
2.74 KB
01/28/2018 09:20:33 PM
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kvm_host.h
19.92 KB
11/01/2022 04:52:05 PM
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kvm_para.h
1.49 KB
01/28/2018 09:20:33 PM
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kvm_ppc.h
34.83 KB
11/01/2022 04:52:05 PM
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📄
libata-portmap.h
249 bytes
01/28/2018 09:20:33 PM
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linkage.h
501 bytes
01/28/2018 09:20:33 PM
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livepatch.h
1.65 KB
01/28/2018 09:20:33 PM
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local.h
3.79 KB
01/28/2018 09:20:33 PM
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lppaca.h
5.02 KB
01/28/2018 09:20:33 PM
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lv1call.h
18.74 KB
01/28/2018 09:20:33 PM
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machdep.h
9.7 KB
11/01/2022 04:52:05 PM
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macio.h
3.89 KB
01/28/2018 09:20:33 PM
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mc146818rtc.h
943 bytes
01/28/2018 09:20:33 PM
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mce.h
5.58 KB
01/28/2018 09:20:33 PM
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mediabay.h
1.34 KB
01/28/2018 09:20:33 PM
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mm-arch-hooks.h
839 bytes
01/28/2018 09:20:33 PM
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mman.h
1.33 KB
01/28/2018 09:20:33 PM
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mmu-40x.h
1.94 KB
01/28/2018 09:20:33 PM
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mmu-44x.h
5.56 KB
01/28/2018 09:20:33 PM
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mmu-8xx.h
8.6 KB
11/01/2022 04:52:05 PM
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mmu-book3e.h
9.47 KB
01/28/2018 09:20:33 PM
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mmu.h
9.2 KB
01/28/2018 09:20:33 PM
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mmu_context.h
6.26 KB
11/01/2022 04:52:05 PM
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mmzone.h
1.08 KB
01/28/2018 09:20:33 PM
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module.h
2.47 KB
01/28/2018 09:20:33 PM
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mpc5121.h
3.82 KB
01/28/2018 09:20:33 PM
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mpc52xx.h
10.85 KB
01/28/2018 09:20:33 PM
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mpc52xx_psc.h
9.89 KB
01/28/2018 09:20:33 PM
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mpc5xxx.h
641 bytes
01/28/2018 09:20:33 PM
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mpc6xx.h
143 bytes
01/28/2018 09:20:33 PM
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mpc8260.h
742 bytes
01/28/2018 09:20:33 PM
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mpc85xx.h
2.52 KB
01/28/2018 09:20:33 PM
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mpic.h
13.97 KB
11/01/2022 04:52:05 PM
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mpic_msgr.h
3.52 KB
01/28/2018 09:20:33 PM
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mpic_timer.h
1.39 KB
01/28/2018 09:20:33 PM
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msi_bitmap.h
1.01 KB
01/28/2018 09:20:33 PM
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nmi.h
238 bytes
11/01/2022 04:52:05 PM
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nohash
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11/17/2022 06:42:21 AM
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nvram.h
3.21 KB
01/28/2018 09:20:33 PM
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ohare.h
1.64 KB
01/28/2018 09:20:33 PM
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opal-api.h
29.34 KB
11/01/2022 04:52:05 PM
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opal.h
16.53 KB
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oprofile_impl.h
3 KB
01/28/2018 09:20:33 PM
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paca.h
8.06 KB
11/01/2022 04:52:05 PM
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page.h
10.65 KB
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page_32.h
1.57 KB
01/28/2018 09:20:33 PM
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page_64.h
2.93 KB
11/01/2022 04:52:05 PM
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parport.h
956 bytes
01/28/2018 09:20:33 PM
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pasemi_dma.h
23.32 KB
01/28/2018 09:20:33 PM
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pci-bridge.h
9.21 KB
11/01/2022 04:52:05 PM
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pci.h
4.58 KB
11/01/2022 04:52:05 PM
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percpu.h
468 bytes
11/01/2022 04:52:05 PM
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perf_event.h
1.23 KB
01/28/2018 09:20:33 PM
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perf_event_fsl_emb.h
1.42 KB
01/28/2018 09:20:33 PM
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perf_event_server.h
6.3 KB
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pgalloc.h
620 bytes
01/28/2018 09:20:33 PM
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pgtable-be-types.h
2.76 KB
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pgtable-types.h
1.94 KB
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pgtable.h
2.45 KB
11/01/2022 04:52:05 PM
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plpar_wrappers.h
8.35 KB
01/28/2018 09:20:33 PM
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pmac_feature.h
13.08 KB
01/28/2018 09:20:33 PM
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pmac_low_i2c.h
3.24 KB
01/28/2018 09:20:33 PM
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pmac_pfunc.h
8.01 KB
01/28/2018 09:20:33 PM
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pmc.h
1.35 KB
01/28/2018 09:20:33 PM
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pmi.h
1.77 KB
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pnv-ocxl.h
1.4 KB
11/01/2022 04:52:05 PM
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pnv-pci.h
3.22 KB
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powernv.h
1.57 KB
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ppc-opcode.h
19.05 KB
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ppc-pci.h
2.69 KB
01/28/2018 09:20:33 PM
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ppc4xx.h
530 bytes
01/28/2018 09:20:33 PM
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ppc4xx_ocm.h
1.41 KB
01/28/2018 09:20:33 PM
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ppc_asm.h
21.63 KB
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probes.h
2.11 KB
01/28/2018 09:20:33 PM
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processor.h
15 KB
11/01/2022 04:52:05 PM
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prom.h
7.17 KB
01/28/2018 09:20:33 PM
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ps3.h
15.44 KB
11/01/2022 04:52:05 PM
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ps3av.h
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Editing: reg_a2.h
Close
/* * Register definitions specific to the A2 core * * Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ #ifndef __ASM_POWERPC_REG_A2_H__ #define __ASM_POWERPC_REG_A2_H__ #define SPRN_TENSR 0x1b5 #define SPRN_TENS 0x1b6 /* Thread ENable Set */ #define SPRN_TENC 0x1b7 /* Thread ENable Clear */ #define SPRN_A2_CCR0 0x3f0 /* Core Configuration Register 0 */ #define SPRN_A2_CCR1 0x3f1 /* Core Configuration Register 1 */ #define SPRN_A2_CCR2 0x3f2 /* Core Configuration Register 2 */ #define SPRN_MMUCR0 0x3fc /* MMU Control Register 0 */ #define SPRN_MMUCR1 0x3fd /* MMU Control Register 1 */ #define SPRN_MMUCR2 0x3fe /* MMU Control Register 2 */ #define SPRN_MMUCR3 0x3ff /* MMU Control Register 3 */ #define SPRN_IAR 0x372 #define SPRN_IUCR0 0x3f3 #define IUCR0_ICBI_ACK 0x1000 #define SPRN_XUCR0 0x3f6 /* Execution Unit Config Register 0 */ #define A2_IERAT_SIZE 16 #define A2_DERAT_SIZE 32 /* A2 MMUCR0 bits */ #define MMUCR0_ECL 0x80000000 /* Extended Class for TLB fills */ #define MMUCR0_TID_NZ 0x40000000 /* TID is non-zero */ #define MMUCR0_TS 0x10000000 /* Translation space for TLB fills */ #define MMUCR0_TGS 0x20000000 /* Guest space for TLB fills */ #define MMUCR0_TLBSEL 0x0c000000 /* TLB or ERAT target for TLB fills */ #define MMUCR0_TLBSEL_U 0x00000000 /* TLBSEL = UTLB */ #define MMUCR0_TLBSEL_I 0x08000000 /* TLBSEL = I-ERAT */ #define MMUCR0_TLBSEL_D 0x0c000000 /* TLBSEL = D-ERAT */ #define MMUCR0_LOCKSRSH 0x02000000 /* Use TLB lock on tlbsx. */ #define MMUCR0_TID_MASK 0x000000ff /* TID field */ /* A2 MMUCR1 bits */ #define MMUCR1_IRRE 0x80000000 /* I-ERAT round robin enable */ #define MMUCR1_DRRE 0x40000000 /* D-ERAT round robin enable */ #define MMUCR1_REE 0x20000000 /* Reference Exception Enable*/ #define MMUCR1_CEE 0x10000000 /* Change exception enable */ #define MMUCR1_CSINV_ALL 0x00000000 /* Inval ERAT on all CS evts */ #define MMUCR1_CSINV_NISYNC 0x04000000 /* Inval ERAT on all ex isync*/ #define MMUCR1_CSINV_NEVER 0x0c000000 /* Don't inval ERAT on CS */ #define MMUCR1_ICTID 0x00080000 /* IERAT class field as TID */ #define MMUCR1_ITTID 0x00040000 /* IERAT thdid field as TID */ #define MMUCR1_DCTID 0x00020000 /* DERAT class field as TID */ #define MMUCR1_DTTID 0x00010000 /* DERAT thdid field as TID */ #define MMUCR1_DCCD 0x00008000 /* DERAT class ignore */ #define MMUCR1_TLBWE_BINV 0x00004000 /* back invalidate on tlbwe */ /* A2 MMUCR2 bits */ #define MMUCR2_PSSEL_SHIFT 4 /* A2 MMUCR3 bits */ #define MMUCR3_THID 0x0000000f /* Thread ID */ /* *** ERAT TLB bits definitions */ #define TLB0_EPN_MASK ASM_CONST(0xfffffffffffff000) #define TLB0_CLASS_MASK ASM_CONST(0x0000000000000c00) #define TLB0_CLASS_00 ASM_CONST(0x0000000000000000) #define TLB0_CLASS_01 ASM_CONST(0x0000000000000400) #define TLB0_CLASS_10 ASM_CONST(0x0000000000000800) #define TLB0_CLASS_11 ASM_CONST(0x0000000000000c00) #define TLB0_V ASM_CONST(0x0000000000000200) #define TLB0_X ASM_CONST(0x0000000000000100) #define TLB0_SIZE_MASK ASM_CONST(0x00000000000000f0) #define TLB0_SIZE_4K ASM_CONST(0x0000000000000010) #define TLB0_SIZE_64K ASM_CONST(0x0000000000000030) #define TLB0_SIZE_1M ASM_CONST(0x0000000000000050) #define TLB0_SIZE_16M ASM_CONST(0x0000000000000070) #define TLB0_SIZE_1G ASM_CONST(0x00000000000000a0) #define TLB0_THDID_MASK ASM_CONST(0x000000000000000f) #define TLB0_THDID_0 ASM_CONST(0x0000000000000001) #define TLB0_THDID_1 ASM_CONST(0x0000000000000002) #define TLB0_THDID_2 ASM_CONST(0x0000000000000004) #define TLB0_THDID_3 ASM_CONST(0x0000000000000008) #define TLB0_THDID_ALL ASM_CONST(0x000000000000000f) #define TLB1_RESVATTR ASM_CONST(0x00f0000000000000) #define TLB1_U0 ASM_CONST(0x0008000000000000) #define TLB1_U1 ASM_CONST(0x0004000000000000) #define TLB1_U2 ASM_CONST(0x0002000000000000) #define TLB1_U3 ASM_CONST(0x0001000000000000) #define TLB1_R ASM_CONST(0x0000800000000000) #define TLB1_C ASM_CONST(0x0000400000000000) #define TLB1_RPN_MASK ASM_CONST(0x000003fffffff000) #define TLB1_W ASM_CONST(0x0000000000000800) #define TLB1_I ASM_CONST(0x0000000000000400) #define TLB1_M ASM_CONST(0x0000000000000200) #define TLB1_G ASM_CONST(0x0000000000000100) #define TLB1_E ASM_CONST(0x0000000000000080) #define TLB1_VF ASM_CONST(0x0000000000000040) #define TLB1_UX ASM_CONST(0x0000000000000020) #define TLB1_SX ASM_CONST(0x0000000000000010) #define TLB1_UW ASM_CONST(0x0000000000000008) #define TLB1_SW ASM_CONST(0x0000000000000004) #define TLB1_UR ASM_CONST(0x0000000000000002) #define TLB1_SR ASM_CONST(0x0000000000000001) /* A2 erativax attributes definitions */ #define ERATIVAX_RS_IS_ALL 0x000 #define ERATIVAX_RS_IS_TID 0x040 #define ERATIVAX_RS_IS_CLASS 0x080 #define ERATIVAX_RS_IS_FULLMATCH 0x0c0 #define ERATIVAX_CLASS_00 0x000 #define ERATIVAX_CLASS_01 0x010 #define ERATIVAX_CLASS_10 0x020 #define ERATIVAX_CLASS_11 0x030 #define ERATIVAX_PSIZE_4K (TLB_PSIZE_4K >> 1) #define ERATIVAX_PSIZE_64K (TLB_PSIZE_64K >> 1) #define ERATIVAX_PSIZE_1M (TLB_PSIZE_1M >> 1) #define ERATIVAX_PSIZE_16M (TLB_PSIZE_16M >> 1) #define ERATIVAX_PSIZE_1G (TLB_PSIZE_1G >> 1) /* A2 eratilx attributes definitions */ #define ERATILX_T_ALL 0 #define ERATILX_T_TID 1 #define ERATILX_T_TGS 2 #define ERATILX_T_FULLMATCH 3 #define ERATILX_T_CLASS0 4 #define ERATILX_T_CLASS1 5 #define ERATILX_T_CLASS2 6 #define ERATILX_T_CLASS3 7 /* XUCR0 bits */ #define XUCR0_TRACE_UM_T0 0x40000000 /* Thread 0 */ #define XUCR0_TRACE_UM_T1 0x20000000 /* Thread 1 */ #define XUCR0_TRACE_UM_T2 0x10000000 /* Thread 2 */ #define XUCR0_TRACE_UM_T3 0x08000000 /* Thread 3 */ /* A2 CCR0 register */ #define A2_CCR0_PME_DISABLED 0x00000000 #define A2_CCR0_PME_SLEEP 0x40000000 #define A2_CCR0_PME_RVW 0x80000000 #define A2_CCR0_PME_DISABLED2 0xc0000000 /* A2 CCR2 register */ #define A2_CCR2_ERAT_ONLY_MODE 0x00000001 #define A2_CCR2_ENABLE_ICSWX 0x00000002 #define A2_CCR2_ENABLE_PC 0x20000000 #define A2_CCR2_ENABLE_TRACE 0x40000000 #endif /* __ASM_POWERPC_REG_A2_H__ */