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linux-headers-4.15.0-197
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powerpc
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include
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asm
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Size
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11/17/2022 06:42:16 AM
rwxr-xr-x
📄
8xx_immap.h
13.77 KB
01/28/2018 09:20:33 PM
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📄
Kbuild
248 bytes
01/28/2018 09:20:33 PM
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accounting.h
1 KB
01/28/2018 09:20:33 PM
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agp.h
525 bytes
01/28/2018 09:20:33 PM
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archrandom.h
1016 bytes
11/01/2022 04:52:05 PM
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asm-compat.h
2.53 KB
01/28/2018 09:20:33 PM
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asm-offsets.h
35 bytes
01/28/2018 09:20:33 PM
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asm-prototypes.h
4.78 KB
11/01/2022 04:52:05 PM
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async_tx.h
1.64 KB
01/28/2018 09:20:33 PM
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atomic.h
13.57 KB
01/28/2018 09:20:33 PM
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backlight.h
1.09 KB
01/28/2018 09:20:33 PM
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barrier.h
3.57 KB
11/01/2022 04:52:05 PM
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bitops.h
7.8 KB
11/01/2022 04:52:05 PM
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book3s
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11/17/2022 06:42:21 AM
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bootx.h
1.12 KB
01/28/2018 09:20:33 PM
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btext.h
926 bytes
01/28/2018 09:20:33 PM
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bug.h
3.55 KB
01/28/2018 09:20:33 PM
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bugs.h
486 bytes
01/28/2018 09:20:33 PM
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cache.h
2.47 KB
11/01/2022 04:52:05 PM
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cacheflush.h
3.76 KB
01/28/2018 09:20:33 PM
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cell-pmu.h
4.04 KB
01/28/2018 09:20:33 PM
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cell-regs.h
9.57 KB
01/28/2018 09:20:33 PM
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checksum.h
5.85 KB
01/28/2018 09:20:33 PM
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cmpxchg.h
12.16 KB
01/28/2018 09:20:33 PM
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📄
code-patching-asm.h
397 bytes
11/01/2022 04:52:05 PM
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code-patching.h
5.01 KB
11/01/2022 04:52:05 PM
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compat.h
6.26 KB
01/28/2018 09:20:33 PM
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context_tracking.h
245 bytes
01/28/2018 09:20:33 PM
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copro.h
769 bytes
01/28/2018 09:20:33 PM
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cpm.h
5.09 KB
01/28/2018 09:20:33 PM
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cpm1.h
21.08 KB
01/28/2018 09:20:33 PM
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cpm2.h
48.43 KB
01/28/2018 09:20:33 PM
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cpu_has_feature.h
1.31 KB
11/01/2022 04:52:05 PM
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cpufeature.h
1.18 KB
01/28/2018 09:20:33 PM
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cpuidle.h
3.31 KB
01/28/2018 09:20:33 PM
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cputable.h
22.56 KB
11/01/2022 04:52:05 PM
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cputhreads.h
2.92 KB
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cputime.h
1.59 KB
01/28/2018 09:20:33 PM
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current.h
835 bytes
01/28/2018 09:20:33 PM
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dbdma.h
3.72 KB
01/28/2018 09:20:33 PM
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dbell.h
2.78 KB
01/28/2018 09:20:33 PM
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dcr-generic.h
1.58 KB
01/28/2018 09:20:33 PM
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dcr-mmio.h
1.68 KB
01/28/2018 09:20:33 PM
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dcr-native.h
4.42 KB
11/01/2022 04:52:05 PM
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dcr-regs.h
5.71 KB
01/28/2018 09:20:33 PM
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dcr.h
2.73 KB
01/28/2018 09:20:33 PM
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debug.h
1.97 KB
01/28/2018 09:20:33 PM
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debugfs.h
489 bytes
01/28/2018 09:20:33 PM
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delay.h
3.42 KB
01/28/2018 09:20:33 PM
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device.h
1.1 KB
01/28/2018 09:20:33 PM
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disassemble.h
2.73 KB
01/28/2018 09:20:33 PM
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dma-mapping.h
4.12 KB
01/28/2018 09:20:33 PM
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dma.h
10.51 KB
01/28/2018 09:20:33 PM
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dt_cpu_ftrs.h
816 bytes
01/28/2018 09:20:33 PM
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edac.h
1.08 KB
01/28/2018 09:20:33 PM
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eeh.h
14.44 KB
01/28/2018 09:20:33 PM
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eeh_event.h
1.36 KB
01/28/2018 09:20:33 PM
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ehv_pic.h
963 bytes
01/28/2018 09:20:33 PM
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elf.h
6.29 KB
01/28/2018 09:20:33 PM
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emergency-restart.h
43 bytes
01/28/2018 09:20:33 PM
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emulated_ops.h
2.58 KB
01/28/2018 09:20:33 PM
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epapr_hcalls.h
16.44 KB
01/28/2018 09:20:33 PM
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exception-64e.h
7.21 KB
01/28/2018 09:20:33 PM
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exception-64s.h
22.72 KB
11/01/2022 04:52:05 PM
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exec.h
246 bytes
01/28/2018 09:20:33 PM
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extable.h
904 bytes
01/28/2018 09:20:33 PM
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fadump.h
6.1 KB
11/01/2022 04:52:05 PM
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fb.h
483 bytes
01/28/2018 09:20:33 PM
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📄
feature-fixups.h
8.76 KB
11/01/2022 04:52:05 PM
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📄
firmware.h
4.71 KB
01/28/2018 09:20:33 PM
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📄
fixmap.h
2.33 KB
01/28/2018 09:20:33 PM
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📄
floppy.h
4.86 KB
01/28/2018 09:20:33 PM
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📄
fs_pd.h
1.02 KB
01/28/2018 09:20:33 PM
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📄
fsl_85xx_cache_sram.h
1.43 KB
01/28/2018 09:20:33 PM
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📄
fsl_gtm.h
1.38 KB
01/28/2018 09:20:33 PM
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📄
fsl_hcalls.h
17.2 KB
01/28/2018 09:20:33 PM
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📄
fsl_lbc.h
10.9 KB
01/28/2018 09:20:33 PM
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fsl_pamu_stash.h
1.1 KB
01/28/2018 09:20:33 PM
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📄
fsl_pm.h
1.36 KB
01/28/2018 09:20:33 PM
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📄
ftrace.h
2.1 KB
01/28/2018 09:20:33 PM
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📄
futex.h
2.4 KB
11/01/2022 04:52:05 PM
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grackle.h
331 bytes
01/28/2018 09:20:33 PM
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hardirq.h
1.15 KB
01/28/2018 09:20:33 PM
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head-64.h
13.86 KB
01/28/2018 09:20:33 PM
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heathrow.h
2.53 KB
01/28/2018 09:20:33 PM
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highmem.h
2.41 KB
01/28/2018 09:20:33 PM
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📄
hmi.h
1.49 KB
11/01/2022 04:52:05 PM
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📄
hugetlb.h
4.73 KB
11/01/2022 04:52:05 PM
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hvcall.h
15.35 KB
11/01/2022 04:52:05 PM
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📄
hvconsole.h
1.37 KB
01/28/2018 09:20:33 PM
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hvcserver.h
2.09 KB
01/28/2018 09:20:33 PM
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📄
hvsi.h
2.78 KB
01/28/2018 09:20:33 PM
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hw_breakpoint.h
3.07 KB
01/28/2018 09:20:33 PM
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hw_irq.h
5.24 KB
11/01/2022 04:52:05 PM
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📄
hydra.h
2.91 KB
01/28/2018 09:20:33 PM
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📄
i8259.h
361 bytes
01/28/2018 09:20:33 PM
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📄
ibmebus.h
2.15 KB
01/28/2018 09:20:33 PM
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📄
icswx.h
4.71 KB
01/28/2018 09:20:33 PM
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📄
ide.h
586 bytes
01/28/2018 09:20:33 PM
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📄
ima.h
772 bytes
01/28/2018 09:20:33 PM
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📄
imc-pmu.h
2.87 KB
01/28/2018 09:20:33 PM
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📄
immap_cpm2.h
10.5 KB
01/28/2018 09:20:33 PM
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📄
io-defs.h
3.09 KB
01/28/2018 09:20:33 PM
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📄
io-workarounds.h
1.54 KB
01/28/2018 09:20:33 PM
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📄
io.h
28.02 KB
11/01/2022 04:52:05 PM
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📄
io_event_irq.h
1.91 KB
01/28/2018 09:20:33 PM
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📄
iommu.h
10.16 KB
01/28/2018 09:20:33 PM
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📄
ipic.h
3.51 KB
01/28/2018 09:20:33 PM
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📄
irq.h
1.83 KB
01/28/2018 09:20:33 PM
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📄
irq_work.h
252 bytes
11/01/2022 04:52:05 PM
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📄
irqflags.h
1.7 KB
01/28/2018 09:20:33 PM
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📄
isa-bridge.h
654 bytes
01/28/2018 09:20:33 PM
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📄
jump_label.h
1.62 KB
01/28/2018 09:20:33 PM
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📄
kdebug.h
291 bytes
01/28/2018 09:20:33 PM
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📄
kdump.h
1.37 KB
01/28/2018 09:20:33 PM
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📄
kexec.h
4.02 KB
11/01/2022 04:52:05 PM
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📄
keylargo.h
10.8 KB
01/28/2018 09:20:33 PM
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kgdb.h
2.06 KB
01/28/2018 09:20:33 PM
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📄
kmap_types.h
434 bytes
01/28/2018 09:20:33 PM
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kprobes.h
3.75 KB
01/28/2018 09:20:33 PM
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📄
kup.h
1021 bytes
11/01/2022 04:52:05 PM
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📄
kvm_asm.h
5.46 KB
11/01/2022 04:52:05 PM
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📄
kvm_book3s.h
12.06 KB
11/01/2022 04:52:05 PM
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📄
kvm_book3s_32.h
1.39 KB
01/28/2018 09:20:33 PM
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kvm_book3s_64.h
12.62 KB
11/01/2022 04:52:05 PM
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kvm_book3s_asm.h
4.4 KB
11/01/2022 04:52:05 PM
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kvm_booke.h
2.68 KB
01/28/2018 09:20:33 PM
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kvm_booke_hv_asm.h
2.03 KB
01/28/2018 09:20:33 PM
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kvm_fpu.h
2.74 KB
01/28/2018 09:20:33 PM
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kvm_host.h
19.92 KB
11/01/2022 04:52:05 PM
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kvm_para.h
1.49 KB
01/28/2018 09:20:33 PM
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kvm_ppc.h
34.83 KB
11/01/2022 04:52:05 PM
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📄
libata-portmap.h
249 bytes
01/28/2018 09:20:33 PM
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linkage.h
501 bytes
01/28/2018 09:20:33 PM
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livepatch.h
1.65 KB
01/28/2018 09:20:33 PM
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local.h
3.79 KB
01/28/2018 09:20:33 PM
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lppaca.h
5.02 KB
01/28/2018 09:20:33 PM
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lv1call.h
18.74 KB
01/28/2018 09:20:33 PM
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machdep.h
9.7 KB
11/01/2022 04:52:05 PM
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macio.h
3.89 KB
01/28/2018 09:20:33 PM
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mc146818rtc.h
943 bytes
01/28/2018 09:20:33 PM
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mce.h
5.58 KB
01/28/2018 09:20:33 PM
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mediabay.h
1.34 KB
01/28/2018 09:20:33 PM
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mm-arch-hooks.h
839 bytes
01/28/2018 09:20:33 PM
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mman.h
1.33 KB
01/28/2018 09:20:33 PM
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mmu-40x.h
1.94 KB
01/28/2018 09:20:33 PM
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mmu-44x.h
5.56 KB
01/28/2018 09:20:33 PM
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mmu-8xx.h
8.6 KB
11/01/2022 04:52:05 PM
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mmu-book3e.h
9.47 KB
01/28/2018 09:20:33 PM
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mmu.h
9.2 KB
01/28/2018 09:20:33 PM
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mmu_context.h
6.26 KB
11/01/2022 04:52:05 PM
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mmzone.h
1.08 KB
01/28/2018 09:20:33 PM
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module.h
2.47 KB
01/28/2018 09:20:33 PM
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mpc5121.h
3.82 KB
01/28/2018 09:20:33 PM
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mpc52xx.h
10.85 KB
01/28/2018 09:20:33 PM
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mpc52xx_psc.h
9.89 KB
01/28/2018 09:20:33 PM
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mpc5xxx.h
641 bytes
01/28/2018 09:20:33 PM
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mpc6xx.h
143 bytes
01/28/2018 09:20:33 PM
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mpc8260.h
742 bytes
01/28/2018 09:20:33 PM
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mpc85xx.h
2.52 KB
01/28/2018 09:20:33 PM
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mpic.h
13.97 KB
11/01/2022 04:52:05 PM
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mpic_msgr.h
3.52 KB
01/28/2018 09:20:33 PM
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mpic_timer.h
1.39 KB
01/28/2018 09:20:33 PM
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msi_bitmap.h
1.01 KB
01/28/2018 09:20:33 PM
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nmi.h
238 bytes
11/01/2022 04:52:05 PM
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nohash
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11/17/2022 06:42:21 AM
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nvram.h
3.21 KB
01/28/2018 09:20:33 PM
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ohare.h
1.64 KB
01/28/2018 09:20:33 PM
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opal-api.h
29.34 KB
11/01/2022 04:52:05 PM
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opal.h
16.53 KB
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oprofile_impl.h
3 KB
01/28/2018 09:20:33 PM
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paca.h
8.06 KB
11/01/2022 04:52:05 PM
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page.h
10.65 KB
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page_32.h
1.57 KB
01/28/2018 09:20:33 PM
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page_64.h
2.93 KB
11/01/2022 04:52:05 PM
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parport.h
956 bytes
01/28/2018 09:20:33 PM
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pasemi_dma.h
23.32 KB
01/28/2018 09:20:33 PM
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pci-bridge.h
9.21 KB
11/01/2022 04:52:05 PM
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pci.h
4.58 KB
11/01/2022 04:52:05 PM
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percpu.h
468 bytes
11/01/2022 04:52:05 PM
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perf_event.h
1.23 KB
01/28/2018 09:20:33 PM
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perf_event_fsl_emb.h
1.42 KB
01/28/2018 09:20:33 PM
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perf_event_server.h
6.3 KB
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pgalloc.h
620 bytes
01/28/2018 09:20:33 PM
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pgtable-be-types.h
2.76 KB
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pgtable-types.h
1.94 KB
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pgtable.h
2.45 KB
11/01/2022 04:52:05 PM
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plpar_wrappers.h
8.35 KB
01/28/2018 09:20:33 PM
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pmac_feature.h
13.08 KB
01/28/2018 09:20:33 PM
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pmac_low_i2c.h
3.24 KB
01/28/2018 09:20:33 PM
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pmac_pfunc.h
8.01 KB
01/28/2018 09:20:33 PM
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pmc.h
1.35 KB
01/28/2018 09:20:33 PM
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pmi.h
1.77 KB
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pnv-ocxl.h
1.4 KB
11/01/2022 04:52:05 PM
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pnv-pci.h
3.22 KB
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powernv.h
1.57 KB
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ppc-opcode.h
19.05 KB
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ppc-pci.h
2.69 KB
01/28/2018 09:20:33 PM
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ppc4xx.h
530 bytes
01/28/2018 09:20:33 PM
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ppc4xx_ocm.h
1.41 KB
01/28/2018 09:20:33 PM
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ppc_asm.h
21.63 KB
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probes.h
2.11 KB
01/28/2018 09:20:33 PM
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processor.h
15 KB
11/01/2022 04:52:05 PM
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prom.h
7.17 KB
01/28/2018 09:20:33 PM
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ps3.h
15.44 KB
11/01/2022 04:52:05 PM
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ps3av.h
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Editing: mmu-8xx.h
Close
/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_POWERPC_MMU_8XX_H_ #define _ASM_POWERPC_MMU_8XX_H_ /* * PPC8xx support */ /* Control/status registers for the MPC8xx. * A write operation to these registers causes serialized access. * During software tablewalk, the registers used perform mask/shift-add * operations when written/read. A TLB entry is created when the Mx_RPN * is written, and the contents of several registers are used to * create the entry. */ #define SPRN_MI_CTR 784 /* Instruction TLB control register */ #define MI_GPM 0x80000000 /* Set domain manager mode */ #define MI_PPM 0x40000000 /* Set subpage protection */ #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ #define MI_RESETVAL 0x00000000 /* Value of register at reset */ /* These are the Ks and Kp from the PowerPC books. For proper operation, * Ks = 0, Kp = 1. */ #define SPRN_MI_AP 786 #define MI_Ks 0x80000000 /* Should not be set */ #define MI_Kp 0x40000000 /* Should always be set */ /* * All pages' PP exec bits are set to 000, which means Execute for Supervisor * and no Execute for User. * Then we use the APG to say whether accesses are according to Page rules, * "all Supervisor" rules (Exec for all) and "all User" rules (Exec for noone) * Therefore, we define 4 APG groups. msb is _PAGE_EXEC, lsb is _PAGE_USER * 0 (00) => Not User, no exec => 11 (all accesses performed as user) * 1 (01) => User but no exec => 11 (all accesses performed as user) * 2 (10) => Not User, exec => 01 (rights according to page definition) * 3 (11) => User, exec => 00 (all accesses performed as supervisor) */ #define MI_APG_INIT 0xf4ffffff /* The effective page number register. When read, contains the information * about the last instruction TLB miss. When MI_RPN is written, bits in * this register are used to create the TLB entry. */ #define SPRN_MI_EPN 787 #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ #define MI_EVALID 0x00000200 /* Entry is valid */ #define MI_ASIDMASK 0x0000000f /* ASID match value */ /* Reset value is undefined */ /* A "level 1" or "segment" or whatever you want to call it register. * For the instruction TLB, it contains bits that get loaded into the * TLB entry when the MI_RPN is written. */ #define SPRN_MI_TWC 789 #define MI_APG 0x000001e0 /* Access protection group (0) */ #define MI_GUARDED 0x00000010 /* Guarded storage */ #define MI_PSMASK 0x0000000c /* Mask of page size bits */ #define MI_PS8MEG 0x0000000c /* 8M page size */ #define MI_PS512K 0x00000004 /* 512K page size */ #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ #define MI_SVALID 0x00000001 /* Segment entry is valid */ /* Reset value is undefined */ /* Real page number. Defined by the pte. Writing this register * causes a TLB entry to be created for the instruction TLB, using * additional information from the MI_EPN, and MI_TWC registers. */ #define SPRN_MI_RPN 790 #define MI_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */ /* Define an RPN value for mapping kernel memory to large virtual * pages for boot initialization. This has real page number of 0, * large page size, shared page, cache enabled, and valid. * Also mark all subpages valid and write access. */ #define MI_BOOTINIT 0x000001fd #define SPRN_MD_CTR 792 /* Data TLB control register */ #define MD_GPM 0x80000000 /* Set domain manager mode */ #define MD_PPM 0x40000000 /* Set subpage protection */ #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ #define MD_RESETVAL 0x04000000 /* Value of register at reset */ #define SPRN_M_CASID 793 /* Address space ID (context) to match */ #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ /* These are the Ks and Kp from the PowerPC books. For proper operation, * Ks = 0, Kp = 1. */ #define SPRN_MD_AP 794 #define MD_Ks 0x80000000 /* Should not be set */ #define MD_Kp 0x40000000 /* Should always be set */ /* * All pages' PP data bits are set to either 000 or 011, which means * respectively RW for Supervisor and no access for User, or RO for * Supervisor and no access for user. * Then we use the APG to say whether accesses are according to Page rules or * "all Supervisor" rules (Access to all) * Therefore, we define 2 APG groups. lsb is _PAGE_USER * 0 => No user => 01 (all accesses performed according to page definition) * 1 => User => 00 (all accesses performed as supervisor * according to page definition) */ #define MD_APG_INIT 0x4fffffff /* The effective page number register. When read, contains the information * about the last instruction TLB miss. When MD_RPN is written, bits in * this register are used to create the TLB entry. */ #define SPRN_MD_EPN 795 #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ #define MD_EVALID 0x00000200 /* Entry is valid */ #define MD_ASIDMASK 0x0000000f /* ASID match value */ /* Reset value is undefined */ /* The pointer to the base address of the first level page table. * During a software tablewalk, reading this register provides the address * of the entry associated with MD_EPN. */ #define SPRN_M_TWB 796 #define M_L1TB 0xfffff000 /* Level 1 table base address */ #define M_L1INDX 0x00000ffc /* Level 1 index, when read */ /* Reset value is undefined */ /* A "level 1" or "segment" or whatever you want to call it register. * For the data TLB, it contains bits that get loaded into the TLB entry * when the MD_RPN is written. It is also provides the hardware assist * for finding the PTE address during software tablewalk. */ #define SPRN_MD_TWC 797 #define MD_L2TB 0xfffff000 /* Level 2 table base address */ #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ #define MD_APG 0x000001e0 /* Access protection group (0) */ #define MD_GUARDED 0x00000010 /* Guarded storage */ #define MD_PSMASK 0x0000000c /* Mask of page size bits */ #define MD_PS8MEG 0x0000000c /* 8M page size */ #define MD_PS512K 0x00000004 /* 512K page size */ #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ #define MD_WT 0x00000002 /* Use writethrough page attribute */ #define MD_SVALID 0x00000001 /* Segment entry is valid */ /* Reset value is undefined */ /* Real page number. Defined by the pte. Writing this register * causes a TLB entry to be created for the data TLB, using * additional information from the MD_EPN, and MD_TWC registers. */ #define SPRN_MD_RPN 798 #define MD_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */ /* This is a temporary storage register that could be used to save * a processor working register during a tablewalk. */ #define SPRN_M_TW 799 #ifndef __ASSEMBLY__ typedef struct { unsigned int id; unsigned int active; unsigned long vdso_base; #ifdef CONFIG_PPC_MM_SLICES u16 user_psize; /* page size index */ u64 low_slices_psize; /* page size encodings */ unsigned char high_slices_psize[0]; unsigned long slb_addr_limit; #endif } mm_context_t; #define PHYS_IMMR_BASE (mfspr(SPRN_IMMR) & 0xfff80000) #define VIRT_IMMR_BASE (__fix_to_virt(FIX_IMMR_BASE)) /* Page size definitions, common between 32 and 64-bit * * shift : is the "PAGE_SHIFT" value for that page size * penc : is the pte encoding mask * */ struct mmu_psize_def { unsigned int shift; /* number of bits */ unsigned int enc; /* PTE encoding */ unsigned int ind; /* Corresponding indirect page size shift */ unsigned int flags; #define MMU_PAGE_SIZE_DIRECT 0x1 /* Supported as a direct size */ #define MMU_PAGE_SIZE_INDIRECT 0x2 /* Supported as an indirect size */ }; extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; static inline int shift_to_mmu_psize(unsigned int shift) { int psize; for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) if (mmu_psize_defs[psize].shift == shift) return psize; return -1; } static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) { if (mmu_psize_defs[mmu_psize].shift) return mmu_psize_defs[mmu_psize].shift; BUG(); } #endif /* !__ASSEMBLY__ */ #if defined(CONFIG_PPC_4K_PAGES) #define mmu_virtual_psize MMU_PAGE_4K #elif defined(CONFIG_PPC_16K_PAGES) #define mmu_virtual_psize MMU_PAGE_16K #else #error "Unsupported PAGE_SIZE" #endif #define mmu_linear_psize MMU_PAGE_8M #endif /* _ASM_POWERPC_MMU_8XX_H_ */