OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:13 AM	rwxr-xr-x
📄 Kbuild	685 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-uaccess.h	4.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro.h	2.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	7.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	542 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	5.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bootparam.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	451 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	969 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheasm.h	3.77 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cacheflush.h	5.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 coprocessor.h	5.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	675 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	1.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	855 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	5.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flat.h	686 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	979 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.59 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 highmem.h	2.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_breakpoint.h	1.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	320 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 initialize_mmu.h	4.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmem_layout.h	2.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	462 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	3.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	525 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mxregs.h	1.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nommu_context.h	602 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	5.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-bridge.h	2.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	108 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	1.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	14.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 platform.h	1.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	7.44 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ptrace.h	3.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 regs.h	3.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 segment.h	376 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	443 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	561 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	502 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	967 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	4.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	412 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	1.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	2.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	601 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	982 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sysmem.h	426 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	3.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	1.79 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tlb.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	5.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	1.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 types.h	501 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	8.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ucontext.h	540 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	864 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	639 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	507 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vectors.h	4.05 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 vga.h	434 bytes	01/28/2018 09:20:33 PM	rw-r--r--

Editing: tlbflush.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2001 - 2013 Tensilica Inc.
 */

#ifndef _XTENSA_TLBFLUSH_H
#define _XTENSA_TLBFLUSH_H

#include <linux/stringify.h>
#include <asm/processor.h>

#define DTLB_WAY_PGD	7

#define ITLB_ARF_WAYS	4
#define DTLB_ARF_WAYS	4

#define ITLB_HIT_BIT	3
#define DTLB_HIT_BIT	4

#ifndef __ASSEMBLY__

/* TLB flushing:
 *
 *  - flush_tlb_all() flushes all processes TLB entries
 *  - flush_tlb_mm(mm) flushes the specified mm context TLB entries
 *  - flush_tlb_page(mm, vmaddr) flushes a single page
 *  - flush_tlb_range(mm, start, end) flushes a range of pages
 */

void local_flush_tlb_all(void);
void local_flush_tlb_mm(struct mm_struct *mm);
void local_flush_tlb_page(struct vm_area_struct *vma,
		unsigned long page);
void local_flush_tlb_range(struct vm_area_struct *vma,
		unsigned long start, unsigned long end);
void local_flush_tlb_kernel_range(unsigned long start, unsigned long end);

#ifdef CONFIG_SMP

void flush_tlb_all(void);
void flush_tlb_mm(struct mm_struct *);
void flush_tlb_page(struct vm_area_struct *, unsigned long);
void flush_tlb_range(struct vm_area_struct *, unsigned long,
		unsigned long);
void flush_tlb_kernel_range(unsigned long start, unsigned long end);

#else /* !CONFIG_SMP */

#define flush_tlb_all()			   local_flush_tlb_all()
#define flush_tlb_mm(mm)		   local_flush_tlb_mm(mm)
#define flush_tlb_page(vma, page)	   local_flush_tlb_page(vma, page)
#define flush_tlb_range(vma, vmaddr, end)  local_flush_tlb_range(vma, vmaddr, \
								 end)
#define flush_tlb_kernel_range(start, end) local_flush_tlb_kernel_range(start, \
									end)

#endif /* CONFIG_SMP */

/* TLB operations. */

static inline unsigned long itlb_probe(unsigned long addr)
{
	unsigned long tmp;
	__asm__ __volatile__("pitlb  %0, %1\n\t" : "=a" (tmp) : "a" (addr));
	return tmp;
}

static inline unsigned long dtlb_probe(unsigned long addr)
{
	unsigned long tmp;
	__asm__ __volatile__("pdtlb  %0, %1\n\t" : "=a" (tmp) : "a" (addr));
	return tmp;
}

static inline void invalidate_itlb_entry (unsigned long probe)
{
	__asm__ __volatile__("iitlb  %0; isync\n\t" : : "a" (probe));
}

static inline void invalidate_dtlb_entry (unsigned long probe)
{
	__asm__ __volatile__("idtlb  %0; dsync\n\t" : : "a" (probe));
}

/* Use the .._no_isync functions with caution.  Generally, these are
 * handy for bulk invalidates followed by a single 'isync'.  The
 * caller must follow up with an 'isync', which can be relatively
 * expensive on some Xtensa implementations.
 */
static inline void invalidate_itlb_entry_no_isync (unsigned entry)
{
	/* Caller must follow up with 'isync'. */
	__asm__ __volatile__ ("iitlb  %0\n" : : "a" (entry) );
}

static inline void invalidate_dtlb_entry_no_isync (unsigned entry)
{
	/* Caller must follow up with 'isync'. */
	__asm__ __volatile__ ("idtlb  %0\n" : : "a" (entry) );
}

static inline void set_itlbcfg_register (unsigned long val)
{
	__asm__ __volatile__("wsr  %0, itlbcfg\n\t" "isync\n\t"
			     : : "a" (val));
}

static inline void set_dtlbcfg_register (unsigned long val)
{
	__asm__ __volatile__("wsr  %0, dtlbcfg; dsync\n\t"
	    		     : : "a" (val));
}

static inline void set_ptevaddr_register (unsigned long val)
{
	__asm__ __volatile__(" wsr  %0, ptevaddr; isync\n"
			     : : "a" (val));
}

static inline unsigned long read_ptevaddr_register (void)
{
	unsigned long tmp;
	__asm__ __volatile__("rsr  %0, ptevaddr\n\t" : "=a" (tmp));
	return tmp;
}

static inline void write_dtlb_entry (pte_t entry, int way)
{
	__asm__ __volatile__("wdtlb  %1, %0; dsync\n\t"
			     : : "r" (way), "r" (entry) );
}

static inline void write_itlb_entry (pte_t entry, int way)
{
	__asm__ __volatile__("witlb  %1, %0; isync\n\t"
	                     : : "r" (way), "r" (entry) );
}

static inline void invalidate_page_directory (void)
{
	invalidate_dtlb_entry (DTLB_WAY_PGD);
	invalidate_dtlb_entry (DTLB_WAY_PGD+1);
	invalidate_dtlb_entry (DTLB_WAY_PGD+2);
}

static inline void invalidate_itlb_mapping (unsigned address)
{
	unsigned long tlb_entry;
	if (((tlb_entry = itlb_probe(address)) & (1 << ITLB_HIT_BIT)) != 0)
		invalidate_itlb_entry(tlb_entry);
}

static inline void invalidate_dtlb_mapping (unsigned address)
{
	unsigned long tlb_entry;
	if (((tlb_entry = dtlb_probe(address)) & (1 << DTLB_HIT_BIT)) != 0)
		invalidate_dtlb_entry(tlb_entry);
}

#define check_pgt_cache()	do { } while (0)

/*
 * DO NOT USE THESE FUNCTIONS.  These instructions aren't part of the Xtensa
 * ISA and exist only for test purposes..
 * You may find it helpful for MMU debugging, however.
 *
 * 'at' is the unmodified input register
 * 'as' is the output register, as follows (specific to the Linux config):
 *
 *      as[31..12] contain the virtual address
 *      as[11..08] are meaningless
 *      as[07..00] contain the asid
 */

static inline unsigned long read_dtlb_virtual (int way)
{
	unsigned long tmp;
	__asm__ __volatile__("rdtlb0  %0, %1\n\t" : "=a" (tmp), "+a" (way));
	return tmp;
}

static inline unsigned long read_dtlb_translation (int way)
{
	unsigned long tmp;
	__asm__ __volatile__("rdtlb1  %0, %1\n\t" : "=a" (tmp), "+a" (way));
	return tmp;
}

static inline unsigned long read_itlb_virtual (int way)
{
	unsigned long tmp;
	__asm__ __volatile__("ritlb0  %0, %1\n\t" : "=a" (tmp), "+a" (way));
	return tmp;
}

static inline unsigned long read_itlb_translation (int way)
{
	unsigned long tmp;
	__asm__ __volatile__("ritlb1  %0, %1\n\t" : "=a" (tmp), "+a" (way));
	return tmp;
}

#endif	/* __ASSEMBLY__ */
#endif	/* _XTENSA_TLBFLUSH_H */