OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:13 AM	rwxr-xr-x
📄 Kbuild	685 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-uaccess.h	4.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro.h	2.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	7.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	542 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	5.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bootparam.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	451 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	969 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheasm.h	3.77 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cacheflush.h	5.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 coprocessor.h	5.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	675 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	1.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	855 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	5.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flat.h	686 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	979 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.59 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 highmem.h	2.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_breakpoint.h	1.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	320 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 initialize_mmu.h	4.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmem_layout.h	2.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	462 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	3.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	525 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mxregs.h	1.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nommu_context.h	602 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	5.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-bridge.h	2.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	108 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	1.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	14.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 platform.h	1.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	7.44 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ptrace.h	3.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 regs.h	3.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 segment.h	376 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	443 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	561 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	502 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	967 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	4.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	412 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	1.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	2.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	601 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	982 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sysmem.h	426 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	3.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	1.79 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tlb.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	5.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	1.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 types.h	501 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	8.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ucontext.h	540 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	864 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	639 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	507 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vectors.h	4.05 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 vga.h	434 bytes	01/28/2018 09:20:33 PM	rw-r--r--

Name

Size

Modified

Perms

📁 ..

05/09/2024 07:14:13 AM

rwxr-xr-x

📄 Kbuild

685 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 asm-offsets.h

35 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 asm-uaccess.h

4.11 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 asmmacro.h

2.76 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 atomic.h

7.38 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 barrier.h

542 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 bitops.h

5.08 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bootparam.h

1.37 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bugs.h

451 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 cache.h

969 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 cacheasm.h

3.77 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 cacheflush.h

5.76 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 checksum.h

6 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cmpxchg.h

3.9 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 coprocessor.h

5.05 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 current.h

675 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 delay.h

1.63 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 dma-mapping.h

855 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 dma.h

1.79 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 elf.h

5.75 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 fixmap.h

2.5 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 flat.h

686 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 ftrace.h

979 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 futex.h

2.59 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 highmem.h

2.33 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 hw_breakpoint.h

1.45 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 hw_irq.h

320 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 initialize_mmu.h

4.58 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 io.h

2.09 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 irq.h

1.46 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 irqflags.h

1.99 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 kmem_layout.h

2.07 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu.h

462 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu_context.h

3.62 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 module.h

525 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 mxregs.h

1.3 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 nommu_context.h

602 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 page.h

5.69 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pci-bridge.h

2.16 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pci.h

1.37 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 perf_event.h

108 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgalloc.h

1.84 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgtable.h

14.89 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 platform.h

1.75 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 processor.h

7.44 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 ptrace.h

3.74 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 regs.h

3.87 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 segment.h

376 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 serial.h

443 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 shmparam.h

561 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 signal.h

502 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 smp.h

967 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 spinlock.h

4.6 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 spinlock_types.h

412 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 stacktrace.h

1.13 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 string.h

2.65 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 switch_to.h

601 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 syscall.h

982 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 sysmem.h

426 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 thread_info.h

3.62 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 timex.h

1.79 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 tlb.h

1.1 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 tlbflush.h

5.53 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 traps.h

1.87 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 types.h

501 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 uaccess.h

8.67 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 ucontext.h

540 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 unaligned.h

864 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 unistd.h

639 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 user.h

507 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 vectors.h

4.05 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 vga.h

434 bytes

01/28/2018 09:20:33 PM

rw-r--r--

Editing: cacheasm.h

/*
 * include/asm-xtensa/cacheasm.h
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2006 Tensilica Inc.
 */

#include <asm/cache.h>
#include <asm/asmmacro.h>
#include <linux/stringify.h>

/*
 * Define cache functions as macros here so that they can be used
 * by the kernel and boot loader. We should consider moving them to a
 * library that can be linked by both.
 *
 * Locking
 *
 *   ___unlock_dcache_all
 *   ___unlock_icache_all
 *
 * Flush and invaldating
 *
 *   ___flush_invalidate_dcache_{all|range|page}
 *   ___flush_dcache_{all|range|page}
 *   ___invalidate_dcache_{all|range|page}
 *   ___invalidate_icache_{all|range|page}
 *
 */

.macro	__loop_cache_unroll ar at insn size line_width max_immed

.if	(1 << (\line_width)) > (\max_immed)
	.set	_reps, 1
	.elseif	(2 << (\line_width)) > (\max_immed)
	.set	_reps, 2
	.else
	.set	_reps, 4
	.endif

__loopi	\ar, \at, \size, (_reps << (\line_width))
	.set	_index, 0
	.rep	_reps
	\insn	\ar, _index << (\line_width)
	.set	_index, _index + 1
	.endr
	__endla	\ar, \at, _reps << (\line_width)

.endm

.macro	__loop_cache_all ar at insn size line_width max_immed

movi	\ar, 0
	__loop_cache_unroll \ar, \at, \insn, \size, \line_width, \max_immed

.endm

.macro	__loop_cache_range ar as at insn line_width

extui	\at, \ar, 0, \line_width
	add	\as, \as, \at

__loops	\ar, \as, \at, \line_width
	\insn	\ar, 0
	__endla	\ar, \at, (1 << (\line_width))

.endm

.macro	__loop_cache_page ar at insn line_width max_immed

__loop_cache_unroll \ar, \at, \insn, PAGE_SIZE, \line_width, \max_immed

.endm

.macro	___unlock_dcache_all ar at

#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE
	__loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE \
		XCHAL_DCACHE_LINEWIDTH 240
#endif

.endm

.macro	___unlock_icache_all ar at

#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
	__loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE \
		XCHAL_ICACHE_LINEWIDTH 240
#endif

.endm

.macro	___flush_invalidate_dcache_all ar at

#if XCHAL_DCACHE_SIZE
	__loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE \
		XCHAL_DCACHE_LINEWIDTH 240
#endif

.endm

.macro	___flush_dcache_all ar at

#if XCHAL_DCACHE_SIZE
	__loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE \
		XCHAL_DCACHE_LINEWIDTH 240
#endif

.endm

.macro	___invalidate_dcache_all ar at

#if XCHAL_DCACHE_SIZE
	__loop_cache_all \ar \at dii XCHAL_DCACHE_SIZE \
			 XCHAL_DCACHE_LINEWIDTH 1020
#endif

.endm

.macro	___invalidate_icache_all ar at

#if XCHAL_ICACHE_SIZE
	__loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \
			 XCHAL_ICACHE_LINEWIDTH 1020
#endif

.endm

.macro	___flush_invalidate_dcache_range ar as at

#if XCHAL_DCACHE_SIZE
	__loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
#endif

.endm

.macro	___flush_dcache_range ar as at

#if XCHAL_DCACHE_SIZE
	__loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
#endif

.endm

.macro	___invalidate_dcache_range ar as at

#if XCHAL_DCACHE_SIZE
	__loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
#endif

.endm

.macro	___invalidate_icache_range ar as at

#if XCHAL_ICACHE_SIZE
	__loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
#endif

.endm

.macro	___flush_invalidate_dcache_page ar as

#if XCHAL_DCACHE_SIZE
	__loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 1020
#endif

.endm

.macro ___flush_dcache_page ar as

#if XCHAL_DCACHE_SIZE
	__loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 1020
#endif

.endm

.macro	___invalidate_dcache_page ar as

#if XCHAL_DCACHE_SIZE
	__loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 1020
#endif

.endm

.macro	___invalidate_icache_page ar as

#if XCHAL_ICACHE_SIZE
	__loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 1020
#endif

.endm