OXIESEC PANEL
- Current Dir:
/
/
usr
/
src
/
linux-headers-4.15.0-213
/
arch
/
xtensa
/
include
/
asm
Server IP: 139.59.38.164
Upload:
Create Dir:
Name
Size
Modified
Perms
📁
..
-
05/09/2024 07:14:13 AM
rwxr-xr-x
📄
Kbuild
685 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
asm-offsets.h
35 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
asm-uaccess.h
4.11 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
asmmacro.h
2.76 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
atomic.h
7.38 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
barrier.h
542 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
bitops.h
5.08 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bootparam.h
1.37 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bugs.h
451 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
cache.h
969 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
cacheasm.h
3.77 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
cacheflush.h
5.76 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
checksum.h
6 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cmpxchg.h
3.9 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
coprocessor.h
5.05 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
current.h
675 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
delay.h
1.63 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
dma-mapping.h
855 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
dma.h
1.79 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
elf.h
5.75 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
fixmap.h
2.5 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
flat.h
686 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
ftrace.h
979 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
futex.h
2.59 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
highmem.h
2.33 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
hw_breakpoint.h
1.45 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
hw_irq.h
320 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
initialize_mmu.h
4.58 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
io.h
2.09 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
irq.h
1.46 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
irqflags.h
1.99 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
kmem_layout.h
2.07 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mmu.h
462 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
mmu_context.h
3.62 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
module.h
525 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
mxregs.h
1.3 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
nommu_context.h
602 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
page.h
5.69 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
pci-bridge.h
2.16 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
pci.h
1.37 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
perf_event.h
108 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
pgalloc.h
1.84 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
pgtable.h
14.89 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
platform.h
1.75 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
processor.h
7.44 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
ptrace.h
3.74 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
regs.h
3.87 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
segment.h
376 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
serial.h
443 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
shmparam.h
561 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
signal.h
502 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
smp.h
967 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
spinlock.h
4.6 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
spinlock_types.h
412 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
stacktrace.h
1.13 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
string.h
2.65 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
switch_to.h
601 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
syscall.h
982 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
sysmem.h
426 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
thread_info.h
3.62 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
timex.h
1.79 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
tlb.h
1.1 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tlbflush.h
5.53 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
traps.h
1.87 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
types.h
501 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
uaccess.h
8.67 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ucontext.h
540 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
unaligned.h
864 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
unistd.h
639 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
user.h
507 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
vectors.h
4.05 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
vga.h
434 bytes
01/28/2018 09:20:33 PM
rw-r--r--
Editing: spinlock.h
Close
/* * include/asm-xtensa/spinlock.h * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2001 - 2005 Tensilica Inc. */ #ifndef _XTENSA_SPINLOCK_H #define _XTENSA_SPINLOCK_H #include <asm/barrier.h> #include <asm/processor.h> /* * spinlock * * There is at most one owner of a spinlock. There are not different * types of spinlock owners like there are for rwlocks (see below). * * When trying to obtain a spinlock, the function "spins" forever, or busy- * waits, until the lock is obtained. When spinning, presumably some other * owner will soon give up the spinlock making it available to others. Use * the trylock functions to avoid spinning forever. * * possible values: * * 0 nobody owns the spinlock * 1 somebody owns the spinlock */ #define arch_spin_is_locked(x) ((x)->slock != 0) static inline void arch_spin_lock(arch_spinlock_t *lock) { unsigned long tmp; __asm__ __volatile__( " movi %0, 0\n" " wsr %0, scompare1\n" "1: movi %0, 1\n" " s32c1i %0, %1, 0\n" " bnez %0, 1b\n" : "=&a" (tmp) : "a" (&lock->slock) : "memory"); } /* Returns 1 if the lock is obtained, 0 otherwise. */ static inline int arch_spin_trylock(arch_spinlock_t *lock) { unsigned long tmp; __asm__ __volatile__( " movi %0, 0\n" " wsr %0, scompare1\n" " movi %0, 1\n" " s32c1i %0, %1, 0\n" : "=&a" (tmp) : "a" (&lock->slock) : "memory"); return tmp == 0 ? 1 : 0; } static inline void arch_spin_unlock(arch_spinlock_t *lock) { unsigned long tmp; __asm__ __volatile__( " movi %0, 0\n" " s32ri %0, %1, 0\n" : "=&a" (tmp) : "a" (&lock->slock) : "memory"); } /* * rwlock * * Read-write locks are really a more flexible spinlock. They allow * multiple readers but only one writer. Write ownership is exclusive * (i.e., all other readers and writers are blocked from ownership while * there is a write owner). These rwlocks are unfair to writers. Writers * can be starved for an indefinite time by readers. * * possible values: * * 0 nobody owns the rwlock * >0 one or more readers own the rwlock * (the positive value is the actual number of readers) * 0x80000000 one writer owns the rwlock, no other writers, no readers */ static inline void arch_write_lock(arch_rwlock_t *rw) { unsigned long tmp; __asm__ __volatile__( " movi %0, 0\n" " wsr %0, scompare1\n" "1: movi %0, 1\n" " slli %0, %0, 31\n" " s32c1i %0, %1, 0\n" " bnez %0, 1b\n" : "=&a" (tmp) : "a" (&rw->lock) : "memory"); } /* Returns 1 if the lock is obtained, 0 otherwise. */ static inline int arch_write_trylock(arch_rwlock_t *rw) { unsigned long tmp; __asm__ __volatile__( " movi %0, 0\n" " wsr %0, scompare1\n" " movi %0, 1\n" " slli %0, %0, 31\n" " s32c1i %0, %1, 0\n" : "=&a" (tmp) : "a" (&rw->lock) : "memory"); return tmp == 0 ? 1 : 0; } static inline void arch_write_unlock(arch_rwlock_t *rw) { unsigned long tmp; __asm__ __volatile__( " movi %0, 0\n" " s32ri %0, %1, 0\n" : "=&a" (tmp) : "a" (&rw->lock) : "memory"); } static inline void arch_read_lock(arch_rwlock_t *rw) { unsigned long tmp; unsigned long result; __asm__ __volatile__( "1: l32i %1, %2, 0\n" " bltz %1, 1b\n" " wsr %1, scompare1\n" " addi %0, %1, 1\n" " s32c1i %0, %2, 0\n" " bne %0, %1, 1b\n" : "=&a" (result), "=&a" (tmp) : "a" (&rw->lock) : "memory"); } /* Returns 1 if the lock is obtained, 0 otherwise. */ static inline int arch_read_trylock(arch_rwlock_t *rw) { unsigned long result; unsigned long tmp; __asm__ __volatile__( " l32i %1, %2, 0\n" " addi %0, %1, 1\n" " bltz %0, 1f\n" " wsr %1, scompare1\n" " s32c1i %0, %2, 0\n" " sub %0, %0, %1\n" "1:\n" : "=&a" (result), "=&a" (tmp) : "a" (&rw->lock) : "memory"); return result == 0; } static inline void arch_read_unlock(arch_rwlock_t *rw) { unsigned long tmp1, tmp2; __asm__ __volatile__( "1: l32i %1, %2, 0\n" " addi %0, %1, -1\n" " wsr %1, scompare1\n" " s32c1i %0, %2, 0\n" " bne %0, %1, 1b\n" : "=&a" (tmp1), "=&a" (tmp2) : "a" (&rw->lock) : "memory"); } #endif /* _XTENSA_SPINLOCK_H */