OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:12 AM	rwxr-xr-x
📄 Kbuild	568 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 arch_gicv3.h	9.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 arch_timer.h	2.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 arm-cci.h	1.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 assembler.h	10.46 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 atomic.h	13.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 auxvec.h	29 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bL_switcher.h	2.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	2.84 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 bitops.h	8.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitrev.h	451 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	2.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	546 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 cache.h	813 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	15.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cachetype.h	2.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	3.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clocksource.h	153 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	6.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 compiler.h	978 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cp15.h	3.84 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpu.h	533 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpufeature.h	1.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpuidle.h	1.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cputype.h	8.42 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cti.h	3.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcc.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	2.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 device.h	771 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 div64.h	3.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-contiguous.h	265 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-iommu.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	7.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	4.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dmi.h	528 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 domain.h	3.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ecard.h	5.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 edac.h	1.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 efi.h	3.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	4.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 entry-macro-multi.S	726 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 exception.h	571 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	375 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fiq.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 firmware.h	1.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	1.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flat.h	915 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	3.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fncpy.h	3.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpstate.h	1.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	1.92 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 futex.h	4.24 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 glue-cache.h	3.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 glue-df.h	2.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 glue-pf.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 glue-proc.h	4.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 glue.h	759 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 gpio.h	693 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	803 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📁 hardware	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 highmem.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb-3level.h	2.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb.h	1.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_breakpoint.h	3.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	349 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hwcap.h	378 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hypervisor.h	140 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	566 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 idmap.h	355 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 insn.h	636 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 io.h	15.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	1015 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 irq_work.h	234 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	3.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	1009 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec-internal.h	272 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 kexec.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	2.72 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kmap_types.h	190 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	2.65 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_arm.h	7.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_asm.h	2.84 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_coproc.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_emulate.h	7.84 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_host.h	10.31 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_hyp.h	4.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_mmio.h	1.34 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_mmu.h	7.27 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 limits.h	166 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	216 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 mach	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 mc146818rtc.h	720 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcpm.h	11.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcs_spinlock.h	570 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 memblock.h	248 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 memory.h	9.95 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmu.h	953 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	3.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	1.57 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mpu.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mtd-xip.h	666 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 neon.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nwflash.h	252 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 opcodes-sec.h	742 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 opcodes-virt.h	1.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 opcodes.h	8.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 outercache.h	3.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page-nommu.h	957 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	3.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 paravirt.h	454 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 patch.h	438 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	956 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu.h	1.56 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 perf_event.h	857 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgalloc.h	3.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-2level-hwdef.h	3.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-2level-types.h	1.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-2level.h	8.51 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtable-3level-hwdef.h	3.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-3level-types.h	1.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-3level.h	9.54 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtable-hwdef.h	467 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-nommu.h	2.51 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgtable.h	11.71 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 probes.h	1.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 proc-fns.h	4.79 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 processor.h	3.4 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 procinfo.h	1.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 prom.h	715 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 psci.h	771 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	4.89 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 sections.h	189 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 set_memory.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	934 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	419 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	500 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	3.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp_plat.h	2.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp_scu.h	1.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp_twd.h	908 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sparsemem.h	716 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spectre.h	906 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 spinlock.h	5.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	541 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackprotector.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	742 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stage2_pgtable.h	2.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 suspend.h	369 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 swab.h	1005 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	1.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sync_bitops.h	1.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	2.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 system_info.h	763 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 system_misc.h	1.14 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tcm.h	937 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 therm.h	655 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	5.2 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 thread_notify.h	1.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	577 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 tlb.h	7.37 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tlbflush.h	17.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tls.h	3.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	1.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 trusted_foundations.h	2.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess-asm.h	2.83 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 uaccess.h	16.22 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ucontext.h	2.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	846 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unified.h	1.61 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 unistd.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unwind.h	1.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uprobes.h	1.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	4.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 v7m.h	2.93 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 vdso.h	507 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 vdso_datapage.h	1.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vfp.h	2.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vfpmacros.h	2.1 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 vga.h	305 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 virt.h	2.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 word-at-a-time.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 xen	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 xor.h	5.22 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: arch_gicv3.h

/*
 * arch/arm/include/asm/arch_gicv3.h
 *
 * Copyright (C) 2015 ARM Ltd.
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_ARCH_GICV3_H
#define __ASM_ARCH_GICV3_H

#ifndef __ASSEMBLY__

#include <linux/io.h>
#include <asm/barrier.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>

#define ICC_EOIR1			__ACCESS_CP15(c12, 0, c12, 1)
#define ICC_DIR				__ACCESS_CP15(c12, 0, c11, 1)
#define ICC_IAR1			__ACCESS_CP15(c12, 0, c12, 0)
#define ICC_SGI1R			__ACCESS_CP15_64(0, c12)
#define ICC_PMR				__ACCESS_CP15(c4, 0, c6, 0)
#define ICC_CTLR			__ACCESS_CP15(c12, 0, c12, 4)
#define ICC_SRE				__ACCESS_CP15(c12, 0, c12, 5)
#define ICC_IGRPEN1			__ACCESS_CP15(c12, 0, c12, 7)
#define ICC_BPR1			__ACCESS_CP15(c12, 0, c12, 3)

#define ICC_HSRE			__ACCESS_CP15(c12, 4, c9, 5)

#define ICH_VSEIR			__ACCESS_CP15(c12, 4, c9, 4)
#define ICH_HCR				__ACCESS_CP15(c12, 4, c11, 0)
#define ICH_VTR				__ACCESS_CP15(c12, 4, c11, 1)
#define ICH_MISR			__ACCESS_CP15(c12, 4, c11, 2)
#define ICH_EISR			__ACCESS_CP15(c12, 4, c11, 3)
#define ICH_ELSR			__ACCESS_CP15(c12, 4, c11, 5)
#define ICH_VMCR			__ACCESS_CP15(c12, 4, c11, 7)

#define __LR0(x)			__ACCESS_CP15(c12, 4, c12, x)
#define __LR8(x)			__ACCESS_CP15(c12, 4, c13, x)

#define ICH_LR0				__LR0(0)
#define ICH_LR1				__LR0(1)
#define ICH_LR2				__LR0(2)
#define ICH_LR3				__LR0(3)
#define ICH_LR4				__LR0(4)
#define ICH_LR5				__LR0(5)
#define ICH_LR6				__LR0(6)
#define ICH_LR7				__LR0(7)
#define ICH_LR8				__LR8(0)
#define ICH_LR9				__LR8(1)
#define ICH_LR10			__LR8(2)
#define ICH_LR11			__LR8(3)
#define ICH_LR12			__LR8(4)
#define ICH_LR13			__LR8(5)
#define ICH_LR14			__LR8(6)
#define ICH_LR15			__LR8(7)

/* LR top half */
#define __LRC0(x)			__ACCESS_CP15(c12, 4, c14, x)
#define __LRC8(x)			__ACCESS_CP15(c12, 4, c15, x)

#define ICH_LRC0			__LRC0(0)
#define ICH_LRC1			__LRC0(1)
#define ICH_LRC2			__LRC0(2)
#define ICH_LRC3			__LRC0(3)
#define ICH_LRC4			__LRC0(4)
#define ICH_LRC5			__LRC0(5)
#define ICH_LRC6			__LRC0(6)
#define ICH_LRC7			__LRC0(7)
#define ICH_LRC8			__LRC8(0)
#define ICH_LRC9			__LRC8(1)
#define ICH_LRC10			__LRC8(2)
#define ICH_LRC11			__LRC8(3)
#define ICH_LRC12			__LRC8(4)
#define ICH_LRC13			__LRC8(5)
#define ICH_LRC14			__LRC8(6)
#define ICH_LRC15			__LRC8(7)

#define __AP0Rx(x)			__ACCESS_CP15(c12, 4, c8, x)
#define ICH_AP0R0			__AP0Rx(0)
#define ICH_AP0R1			__AP0Rx(1)
#define ICH_AP0R2			__AP0Rx(2)
#define ICH_AP0R3			__AP0Rx(3)

#define __AP1Rx(x)			__ACCESS_CP15(c12, 4, c9, x)
#define ICH_AP1R0			__AP1Rx(0)
#define ICH_AP1R1			__AP1Rx(1)
#define ICH_AP1R2			__AP1Rx(2)
#define ICH_AP1R3			__AP1Rx(3)

/* A32-to-A64 mappings used by VGIC save/restore */

#define CPUIF_MAP(a32, a64)			\
static inline void write_ ## a64(u32 val)	\
{						\
	write_sysreg(val, a32);			\
}						\
static inline u32 read_ ## a64(void)		\
{						\
	return read_sysreg(a32); 		\
}						\

#define CPUIF_MAP_LO_HI(a32lo, a32hi, a64)	\
static inline void write_ ## a64(u64 val)	\
{						\
	write_sysreg(lower_32_bits(val), a32lo);\
	write_sysreg(upper_32_bits(val), a32hi);\
}						\
static inline u64 read_ ## a64(void)		\
{						\
	u64 val = read_sysreg(a32lo);		\
						\
	val |=	(u64)read_sysreg(a32hi) << 32;	\
						\
	return val; 				\
}

CPUIF_MAP(ICH_HCR, ICH_HCR_EL2)
CPUIF_MAP(ICH_VTR, ICH_VTR_EL2)
CPUIF_MAP(ICH_MISR, ICH_MISR_EL2)
CPUIF_MAP(ICH_EISR, ICH_EISR_EL2)
CPUIF_MAP(ICH_ELSR, ICH_ELSR_EL2)
CPUIF_MAP(ICH_VMCR, ICH_VMCR_EL2)
CPUIF_MAP(ICH_AP0R3, ICH_AP0R3_EL2)
CPUIF_MAP(ICH_AP0R2, ICH_AP0R2_EL2)
CPUIF_MAP(ICH_AP0R1, ICH_AP0R1_EL2)
CPUIF_MAP(ICH_AP0R0, ICH_AP0R0_EL2)
CPUIF_MAP(ICH_AP1R3, ICH_AP1R3_EL2)
CPUIF_MAP(ICH_AP1R2, ICH_AP1R2_EL2)
CPUIF_MAP(ICH_AP1R1, ICH_AP1R1_EL2)
CPUIF_MAP(ICH_AP1R0, ICH_AP1R0_EL2)
CPUIF_MAP(ICC_HSRE, ICC_SRE_EL2)
CPUIF_MAP(ICC_SRE, ICC_SRE_EL1)

CPUIF_MAP_LO_HI(ICH_LR15, ICH_LRC15, ICH_LR15_EL2)
CPUIF_MAP_LO_HI(ICH_LR14, ICH_LRC14, ICH_LR14_EL2)
CPUIF_MAP_LO_HI(ICH_LR13, ICH_LRC13, ICH_LR13_EL2)
CPUIF_MAP_LO_HI(ICH_LR12, ICH_LRC12, ICH_LR12_EL2)
CPUIF_MAP_LO_HI(ICH_LR11, ICH_LRC11, ICH_LR11_EL2)
CPUIF_MAP_LO_HI(ICH_LR10, ICH_LRC10, ICH_LR10_EL2)
CPUIF_MAP_LO_HI(ICH_LR9, ICH_LRC9, ICH_LR9_EL2)
CPUIF_MAP_LO_HI(ICH_LR8, ICH_LRC8, ICH_LR8_EL2)
CPUIF_MAP_LO_HI(ICH_LR7, ICH_LRC7, ICH_LR7_EL2)
CPUIF_MAP_LO_HI(ICH_LR6, ICH_LRC6, ICH_LR6_EL2)
CPUIF_MAP_LO_HI(ICH_LR5, ICH_LRC5, ICH_LR5_EL2)
CPUIF_MAP_LO_HI(ICH_LR4, ICH_LRC4, ICH_LR4_EL2)
CPUIF_MAP_LO_HI(ICH_LR3, ICH_LRC3, ICH_LR3_EL2)
CPUIF_MAP_LO_HI(ICH_LR2, ICH_LRC2, ICH_LR2_EL2)
CPUIF_MAP_LO_HI(ICH_LR1, ICH_LRC1, ICH_LR1_EL2)
CPUIF_MAP_LO_HI(ICH_LR0, ICH_LRC0, ICH_LR0_EL2)

#define read_gicreg(r)                 read_##r()
#define write_gicreg(v, r)             write_##r(v)

/* Low-level accessors */

static inline void gic_write_eoir(u32 irq)
{
	write_sysreg(irq, ICC_EOIR1);
	isb();
}

static inline void gic_write_dir(u32 val)
{
	write_sysreg(val, ICC_DIR);
	isb();
}

static inline u32 gic_read_iar(void)
{
	u32 irqstat = read_sysreg(ICC_IAR1);

dsb(sy);

return irqstat;
}

static inline void gic_write_pmr(u32 val)
{
	write_sysreg(val, ICC_PMR);
}

static inline void gic_write_ctlr(u32 val)
{
	write_sysreg(val, ICC_CTLR);
	isb();
}

static inline u32 gic_read_ctlr(void)
{
	return read_sysreg(ICC_CTLR);
}

static inline void gic_write_grpen1(u32 val)
{
	write_sysreg(val, ICC_IGRPEN1);
	isb();
}

static inline void gic_write_sgi1r(u64 val)
{
	write_sysreg(val, ICC_SGI1R);
}

static inline u32 gic_read_sre(void)
{
	return read_sysreg(ICC_SRE);
}

static inline void gic_write_sre(u32 val)
{
	write_sysreg(val, ICC_SRE);
	isb();
}

static inline void gic_write_bpr1(u32 val)
{
	write_sysreg(val, ICC_BPR1);
}

/*
 * Even in 32bit systems that use LPAE, there is no guarantee that the I/O
 * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
 * make much sense.
 * Moreover, 64bit I/O emulation is extremely difficult to implement on
 * AArch32, since the syndrome register doesn't provide any information for
 * them.
 * Consequently, the following IO helpers use 32bit accesses.
 */
static inline void __gic_writeq_nonatomic(u64 val, volatile void __iomem *addr)
{
	writel_relaxed((u32)val, addr);
	writel_relaxed((u32)(val >> 32), addr + 4);
}

static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr)
{
	u64 val;

val = readl_relaxed(addr);
	val |= (u64)readl_relaxed(addr + 4) << 32;
	return val;
}

#define gic_flush_dcache_to_poc(a,l)    __cpuc_flush_dcache_area((a), (l))

/*
 *  GICD_IROUTERn, contain the affinity values associated to each interrupt.
 *  The upper-word (aff3) will always be 0, so there is no need for a lock.
 */
#define gic_write_irouter(v, c)		__gic_writeq_nonatomic(v, c)

/*
 * GICR_TYPER is an ID register and doesn't need atomicity.
 */
#define gic_read_typer(c)		__gic_readq_nonatomic(c)

/*
 * GITS_BASER - hi and lo bits may be accessed independently.
 */
#define gits_read_baser(c)		__gic_readq_nonatomic(c)
#define gits_write_baser(v, c)		__gic_writeq_nonatomic(v, c)

/*
 * GICR_PENDBASER and GICR_PROPBASE are changed with LPIs disabled, so they
 * won't be being used during any updates and can be changed non-atomically
 */
#define gicr_read_propbaser(c)		__gic_readq_nonatomic(c)
#define gicr_write_propbaser(v, c)	__gic_writeq_nonatomic(v, c)
#define gicr_read_pendbaser(c)		__gic_readq_nonatomic(c)
#define gicr_write_pendbaser(v, c)	__gic_writeq_nonatomic(v, c)

/*
 * GICR_xLPIR - only the lower bits are significant
 */
#define gic_read_lpir(c)		readl_relaxed(c)
#define gic_write_lpir(v, c)		writel_relaxed(lower_32_bits(v), c)

/*
 * GITS_TYPER is an ID register and doesn't need atomicity.
 */
#define gits_read_typer(c)		__gic_readq_nonatomic(c)

/*
 * GITS_CBASER - hi and lo bits may be accessed independently.
 */
#define gits_read_cbaser(c)		__gic_readq_nonatomic(c)
#define gits_write_cbaser(v, c)		__gic_writeq_nonatomic(v, c)

/*
 * GITS_CWRITER - hi and lo bits may be accessed independently.
 */
#define gits_write_cwriter(v, c)	__gic_writeq_nonatomic(v, c)

/*
 * GITS_VPROPBASER - hi and lo bits may be accessed independently.
 */
#define gits_write_vpropbaser(v, c)	__gic_writeq_nonatomic(v, c)

/*
 * GITS_VPENDBASER - the Valid bit must be cleared before changing
 * anything else.
 */
static inline void gits_write_vpendbaser(u64 val, void * __iomem addr)
{
	u32 tmp;

tmp = readl_relaxed(addr + 4);
	if (tmp & (GICR_VPENDBASER_Valid >> 32)) {
		tmp &= ~(GICR_VPENDBASER_Valid >> 32);
		writel_relaxed(tmp, addr + 4);
	}

/*
	 * Use the fact that __gic_writeq_nonatomic writes the second
	 * half of the 64bit quantity after the first.
	 */
	__gic_writeq_nonatomic(val, addr);
}

#define gits_read_vpendbaser(c)		__gic_readq_nonatomic(c)

#endif /* !__ASSEMBLY__ */
#endif /* !__ASM_ARCH_GICV3_H */