OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 Kbuild	294 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 a.out-core.h	1.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 acenv.h	1.56 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 acpi.h	4.76 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 agp.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 alternative-asm.h	2.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 alternative.h	8.28 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 amd_nb.h	2.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 apb_timer.h	1.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 apic.h	14.53 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 apic_flat_64.h	151 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 apicdef.h	11.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 apm.h	1.8 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 arch_hweight.h	1.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 archrandom.h	3.03 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	946 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm.h	4.97 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 atomic.h	6.02 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 atomic64_32.h	8.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic64_64.h	6.31 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 barrier.h	3.6 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bios_ebda.h	914 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	13.78 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 boot.h	1.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bootparam_utils.h	2.86 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bug.h	2.07 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bugs.h	493 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	641 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	306 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheinfo.h	209 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 calgary.h	2.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ce4100.h	121 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	133 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum_32.h	4.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum_64.h	5.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clocksource.h	488 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmdline.h	302 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	7.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg_32.h	3.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg_64.h	543 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat.h	7.37 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpu.h	975 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu_device_id.h	1.38 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpu_entry_area.h	2.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpufeature.h	7.75 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpufeatures.h	24.62 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpumask.h	408 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 crash.h	320 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📁 crypto	-	11/17/2022 06:42:22 AM	rwxr-xr-x
📄 current.h	443 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 debugreg.h	2.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	208 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 desc.h	11.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 desc_defs.h	3.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 device.h	568 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 disabled-features.h	2.31 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 div64.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	2.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	9.58 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 dmi.h	556 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 dwarf2.h	2.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 e820	-	11/17/2022 06:42:22 AM	rwxr-xr-x
📄 edac.h	474 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 efi.h	6.9 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 elf.h	10.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 emergency-restart.h	202 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 entry_arch.h	1.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 espfix.h	426 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 exec.h	37 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 export.h	120 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable.h	1.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	540 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	6.04 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 floppy.h	6.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 fpu	-	11/17/2022 06:42:22 AM	rwxr-xr-x
📄 frame.h	815 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	1.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gart.h	2.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 genapic.h	22 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 geode.h	842 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	2.3 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 highmem.h	2.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hpet.h	3.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_breakpoint.h	1.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	3.85 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hypervisor.h	1.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i8259.h	1.93 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ia32.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ia32_unistd.h	313 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 imr.h	1.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 inat.h	6.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 inat_types.h	1013 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 init.h	632 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 insn-eval.h	837 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 insn.h	7.46 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 inst.h	5.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel-family.h	3.29 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 intel-mid.h	4.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_ds.h	793 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_mid_vrtc.h	326 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_pmc_ipc.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_pt.h	292 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_punit_ipc.h	4.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_rdt_sched.h	2.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_scu_ipc.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_telemetry.h	3.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 invpcid.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	12.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io_apic.h	5.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 iomap.h	1.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 iommu.h	392 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 iommu_table.h	3.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 iosf_mbi.h	5.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ipi.h	2.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_regs.h	679 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_remapping.h	2.96 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 irq_vectors.h	4.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_work.h	397 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqdomain.h	1.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	4.38 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ist.h	735 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	2.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kasan.h	966 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kaslr.h	424 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kbdleds.h	454 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug.h	752 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec-bzimage64.h	189 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	6.69 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kgdb.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	289 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	3.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_emulate.h	15.23 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_guest.h	172 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_host.h	42.72 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_page_track.h	2.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_para.h	3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvmclock.h	170 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	581 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 livepatch.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 local.h	3.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 local64.h	33 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mach_timer.h	1.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mach_traps.h	1013 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 math_emu.h	395 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc.h	2.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mce.h	12.54 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mem_encrypt.h	2.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 microcode.h	4.14 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 microcode_amd.h	1.41 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 microcode_intel.h	2.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 misc.h	143 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmconfig.h	374 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	10.27 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mmx.h	337 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone.h	129 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone_32.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone_64.h	430 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	2.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpspec.h	3.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpspec_def.h	3.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpx.h	2.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mshyperv.h	10.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msi.h	392 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 msidef.h	1.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msr-index.h	30.36 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 msr-trace.h	1.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msr.h	10.85 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mtrr.h	4.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mwait.h	3.74 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 nmi.h	1.39 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 nops.h	4.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nospec-branch.h	10.87 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 numa.h	2.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 numa_32.h	256 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 numachip	-	11/17/2022 06:42:22 AM	rwxr-xr-x
📄 olpc.h	3.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 olpc_ofw.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 orc_lookup.h	1.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 orc_types.h	3.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	2.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_32.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_32_types.h	1.7 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 page_64.h	1.42 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 page_64_types.h	2.34 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 page_types.h	2.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 paravirt.h	23.31 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 paravirt_types.h	22.15 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 parport.h	314 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pat.h	768 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 pci-direct.h	995 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 pci-functions.h	654 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	3.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci_64.h	684 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci_x86.h	5.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu.h	18.97 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 perf_event.h	8.82 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 perf_event_p4.h	26.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	5.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-2level.h	2.75 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable-2level_types.h	867 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable-3level.h	10.24 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable-3level_types.h	1.06 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable-invert.h	1.07 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable.h	33.91 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable_32.h	3.1 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable_32_types.h	2.01 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable_64.h	7.37 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable_64_types.h	3.67 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable_types.h	16.75 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pkeys.h	3.17 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 platform_sst_audio.h	3.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm-trace.h	611 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 posix_types.h	144 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 preempt.h	3.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 probe_roms.h	273 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor-cyrix.h	879 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor-flags.h	1.71 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 processor.h	24.54 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 prom.h	1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 proto.h	1003 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 pti.h	369 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 ptrace.h	8.52 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 purgatory.h	571 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pvclock-abi.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pvclock.h	2.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 qrwlock.h	199 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 qspinlock.h	2.54 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 qspinlock_paravirt.h	1.85 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 realmode.h	1.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reboot.h	850 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 reboot_fixups.h	183 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 refcount.h	2.83 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 required-features.h	2.81 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 rio.h	2.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rmwcc.h	1.62 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 rwsem.h	7.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seccomp.h	510 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	465 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 segment.h	9.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 set_memory.h	3.86 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 setup.h	3.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup_arch.h	77 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	193 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sigcontext.h	261 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sigframe.h	2.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sighandling.h	649 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	2.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 simd.h	287 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smap.h	1.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	4.73 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 sparsemem.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spec-ctrl.h	2.81 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 special_insns.h	5.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	719 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sta2x11.h	352 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackprotector.h	4.13 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 stacktrace.h	2.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	129 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string_32.h	7.74 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 string_64.h	3.56 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 suspend.h	131 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 suspend_32.h	822 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 suspend_64.h	1.79 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 svm.h	7.06 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 swiotlb.h	991 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	2.98 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 sync_bitops.h	3.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sys_ia32.h	1.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	5.14 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 syscalls.h	1.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sysfb.h	2.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tce.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 text-patching.h	2.3 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 thread_info.h	9.33 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 time.h	331 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 timer.h	1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	546 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 tlb.h	1.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbbatch.h	332 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	17.09 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 topology.h	4.84 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 trace	-	11/17/2022 06:42:22 AM	rwxr-xr-x
📄 trace_clock.h	406 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	5.74 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tsc.h	1.93 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 uaccess.h	21.69 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 uaccess_32.h	1.54 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 uaccess_64.h	5.32 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 umip.h	329 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	345 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	1.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unwind.h	3.13 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 unwind_hints.h	3.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uprobes.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	2.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 user32.h	2.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 user_32.h	4.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 user_64.h	5.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 uv	-	11/17/2022 06:42:22 AM	rwxr-xr-x
📄 vdso.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	740 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vgtod.h	2.13 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 virtext.h	2.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vm86.h	2.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vmx.h	23.5 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 vsyscall.h	635 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vvar.h	1.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 word-at-a-time.h	2.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 x86_init.h	9.25 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 xen	-	11/17/2022 06:42:22 AM	rwxr-xr-x
📄 xor.h	10.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 xor_32.h	14.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 xor_64.h	716 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 xor_avx.h	4.5 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: pgtable-3level.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_PGTABLE_3LEVEL_H
#define _ASM_X86_PGTABLE_3LEVEL_H

#include <asm/atomic64_32.h>

/*
 * Intel Physical Address Extension (PAE) Mode - three-level page
 * tables on PPro+ CPUs.
 *
 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
 */

#define pte_ERROR(e)							\
	pr_err("%s:%d: bad pte %p(%08lx%08lx)\n",			\
	       __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
#define pmd_ERROR(e)							\
	pr_err("%s:%d: bad pmd %p(%016Lx)\n",				\
	       __FILE__, __LINE__, &(e), pmd_val(e))
#define pgd_ERROR(e)							\
	pr_err("%s:%d: bad pgd %p(%016Lx)\n",				\
	       __FILE__, __LINE__, &(e), pgd_val(e))

/* Rules for using set_pte: the pte being assigned *must* be
 * either not present or in a state where the hardware will
 * not attempt to update the pte.  In places where this is
 * not possible, use pte_get_and_clear to obtain the old pte
 * value and then use set_pte to update it.  -ben
 */
static inline void native_set_pte(pte_t *ptep, pte_t pte)
{
	ptep->pte_high = pte.pte_high;
	smp_wmb();
	ptep->pte_low = pte.pte_low;
}

#define pmd_read_atomic pmd_read_atomic
/*
 * pte_offset_map_lock on 32bit PAE kernels was reading the pmd_t with
 * a "*pmdp" dereference done by gcc. Problem is, in certain places
 * where pte_offset_map_lock is called, concurrent page faults are
 * allowed, if the mmap_sem is hold for reading. An example is mincore
 * vs page faults vs MADV_DONTNEED. On the page fault side
 * pmd_populate rightfully does a set_64bit, but if we're reading the
 * pmd_t with a "*pmdp" on the mincore side, a SMP race can happen
 * because gcc will not read the 64bit of the pmd atomically. To fix
 * this all places running pmd_offset_map_lock() while holding the
 * mmap_sem in read mode, shall read the pmdp pointer using this
 * function to know if the pmd is null nor not, and in turn to know if
 * they can run pmd_offset_map_lock or pmd_trans_huge or other pmd
 * operations.
 *
 * Without THP if the mmap_sem is hold for reading, the pmd can only
 * transition from null to not null while pmd_read_atomic runs. So
 * we can always return atomic pmd values with this function.
 *
 * With THP if the mmap_sem is hold for reading, the pmd can become
 * trans_huge or none or point to a pte (and in turn become "stable")
 * at any time under pmd_read_atomic. We could read it really
 * atomically here with a atomic64_read for the THP enabled case (and
 * it would be a whole lot simpler), but to avoid using cmpxchg8b we
 * only return an atomic pmdval if the low part of the pmdval is later
 * found stable (i.e. pointing to a pte). And we're returning a none
 * pmdval if the low part of the pmd is none. In some cases the high
 * and low part of the pmdval returned may not be consistent if THP is
 * enabled (the low part may point to previously mapped hugepage,
 * while the high part may point to a more recently mapped hugepage),
 * but pmd_none_or_trans_huge_or_clear_bad() only needs the low part
 * of the pmd to be read atomically to decide if the pmd is unstable
 * or not, with the only exception of when the low part of the pmd is
 * zero in which case we return a none pmd.
 */
static inline pmd_t pmd_read_atomic(pmd_t *pmdp)
{
	pmdval_t ret;
	u32 *tmp = (u32 *)pmdp;

ret = (pmdval_t) (*tmp);
	if (ret) {
		/*
		 * If the low part is null, we must not read the high part
		 * or we can end up with a partial pmd.
		 */
		smp_rmb();
		ret |= ((pmdval_t)*(tmp + 1)) << 32;
	}

return (pmd_t) { ret };
}

static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
{
	set_64bit((unsigned long long *)(ptep), native_pte_val(pte));
}

static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
{
	set_64bit((unsigned long long *)(pmdp), native_pmd_val(pmd));
}

static inline void native_set_pud(pud_t *pudp, pud_t pud)
{
#ifdef CONFIG_PAGE_TABLE_ISOLATION
	pud.p4d.pgd = pti_set_user_pgtbl(&pudp->p4d.pgd, pud.p4d.pgd);
#endif
	set_64bit((unsigned long long *)(pudp), native_pud_val(pud));
}

/*
 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
 * entry, so clear the bottom half first and enforce ordering with a compiler
 * barrier.
 */
static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
				    pte_t *ptep)
{
	ptep->pte_low = 0;
	smp_wmb();
	ptep->pte_high = 0;
}

static inline void native_pmd_clear(pmd_t *pmd)
{
	u32 *tmp = (u32 *)pmd;
	*tmp = 0;
	smp_wmb();
	*(tmp + 1) = 0;
}

static inline void native_pud_clear(pud_t *pudp)
{
}

static inline void pud_clear(pud_t *pudp)
{
	set_pud(pudp, __pud(0));

/*
	 * According to Intel App note "TLBs, Paging-Structure Caches,
	 * and Their Invalidation", April 2007, document 317080-001,
	 * section 8.1: in PAE mode we explicitly have to flush the
	 * TLB via cr3 if the top-level pgd is changed...
	 *
	 * Currently all places where pud_clear() is called either have
	 * flush_tlb_mm() followed or don't need TLB flush (x86_64 code or
	 * pud_clear_bad()), so we don't need TLB flush here.
	 */
}

#ifdef CONFIG_SMP
static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
{
	pte_t res;

res.pte = (pteval_t)atomic64_xchg((atomic64_t *)ptep, 0);

return res;
}
#else
#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
#endif

union split_pmd {
	struct {
		u32 pmd_low;
		u32 pmd_high;
	};
	pmd_t pmd;
};

#ifdef CONFIG_SMP
static inline pmd_t native_pmdp_get_and_clear(pmd_t *pmdp)
{
	union split_pmd res, *orig = (union split_pmd *)pmdp;

/* xchg acts as a barrier before setting of the high bits */
	res.pmd_low = xchg(&orig->pmd_low, 0);
	res.pmd_high = orig->pmd_high;
	orig->pmd_high = 0;

return res.pmd;
}
#else
#define native_pmdp_get_and_clear(xp) native_local_pmdp_get_and_clear(xp)
#endif

#ifndef pmdp_establish
#define pmdp_establish pmdp_establish
static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
		unsigned long address, pmd_t *pmdp, pmd_t pmd)
{
	pmd_t old;

/*
	 * If pmd has present bit cleared we can get away without expensive
	 * cmpxchg64: we can update pmdp half-by-half without racing with
	 * anybody.
	 */
	if (!(pmd_val(pmd) & _PAGE_PRESENT)) {
		union split_pmd old, new, *ptr;

ptr = (union split_pmd *)pmdp;

new.pmd = pmd;

/* xchg acts as a barrier before setting of the high bits */
		old.pmd_low = xchg(&ptr->pmd_low, new.pmd_low);
		old.pmd_high = ptr->pmd_high;
		ptr->pmd_high = new.pmd_high;
		return old.pmd;
	}

do {
		old = *pmdp;
	} while (cmpxchg64(&pmdp->pmd, old.pmd, pmd.pmd) != old.pmd);

return old;
}
#endif

#ifdef CONFIG_SMP
union split_pud {
	struct {
		u32 pud_low;
		u32 pud_high;
	};
	pud_t pud;
};

static inline pud_t native_pudp_get_and_clear(pud_t *pudp)
{
	union split_pud res, *orig = (union split_pud *)pudp;

#ifdef CONFIG_PAGE_TABLE_ISOLATION
	pti_set_user_pgtbl(&pudp->p4d.pgd, __pgd(0));
#endif

/* xchg acts as a barrier before setting of the high bits */
	res.pud_low = xchg(&orig->pud_low, 0);
	res.pud_high = orig->pud_high;
	orig->pud_high = 0;

return res.pud;
}
#else
#define native_pudp_get_and_clear(xp) native_local_pudp_get_and_clear(xp)
#endif

/* Encode and de-code a swap entry */
#define SWP_TYPE_BITS		5

#define SWP_OFFSET_FIRST_BIT	(_PAGE_BIT_PROTNONE + 1)

/* We always extract/encode the offset by shifting it all the way up, and then down again */
#define SWP_OFFSET_SHIFT	(SWP_OFFSET_FIRST_BIT + SWP_TYPE_BITS)

#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5)
#define __swp_type(x)			(((x).val) & 0x1f)
#define __swp_offset(x)			((x).val >> 5)
#define __swp_entry(type, offset)	((swp_entry_t){(type) | (offset) << 5})

/*
 * Normally, __swp_entry() converts from arch-independent swp_entry_t to
 * arch-dependent swp_entry_t, and __swp_entry_to_pte() just stores the result
 * to pte. But here we have 32bit swp_entry_t and 64bit pte, and need to use the
 * whole 64 bits. Thus, we shift the "real" arch-dependent conversion to
 * __swp_entry_to_pte() through the following helper macro based on 64bit
 * __swp_entry().
 */
#define __swp_pteval_entry(type, offset) ((pteval_t) { \
	(~(pteval_t)(offset) << SWP_OFFSET_SHIFT >> SWP_TYPE_BITS) \
	| ((pteval_t)(type) << (64 - SWP_TYPE_BITS)) })

#define __swp_entry_to_pte(x)	((pte_t){ .pte = \
		__swp_pteval_entry(__swp_type(x), __swp_offset(x)) })
/*
 * Analogically, __pte_to_swp_entry() doesn't just extract the arch-dependent
 * swp_entry_t, but also has to convert it from 64bit to the 32bit
 * intermediate representation, using the following macros based on 64bit
 * __swp_type() and __swp_offset().
 */
#define __pteval_swp_type(x) ((unsigned long)((x).pte >> (64 - SWP_TYPE_BITS)))
#define __pteval_swp_offset(x) ((unsigned long)(~((x).pte) << SWP_TYPE_BITS >> SWP_OFFSET_SHIFT))

#define __pte_to_swp_entry(pte)	(__swp_entry(__pteval_swp_type(pte), \
					     __pteval_swp_offset(pte)))

#define gup_get_pte gup_get_pte
/*
 * WARNING: only to be used in the get_user_pages_fast() implementation.
 *
 * With get_user_pages_fast(), we walk down the pagetables without taking
 * any locks.  For this we would like to load the pointers atomically,
 * but that is not possible (without expensive cmpxchg8b) on PAE.  What
 * we do have is the guarantee that a PTE will only either go from not
 * present to present, or present to not present or both -- it will not
 * switch to a completely different present page without a TLB flush in
 * between; something that we are blocking by holding interrupts off.
 *
 * Setting ptes from not present to present goes:
 *
 *   ptep->pte_high = h;
 *   smp_wmb();
 *   ptep->pte_low = l;
 *
 * And present to not present goes:
 *
 *   ptep->pte_low = 0;
 *   smp_wmb();
 *   ptep->pte_high = 0;
 *
 * We must ensure here that the load of pte_low sees 'l' iff pte_high
 * sees 'h'. We load pte_high *after* loading pte_low, which ensures we
 * don't see an older value of pte_high.  *Then* we recheck pte_low,
 * which ensures that we haven't picked up a changed pte high. We might
 * have gotten rubbish values from pte_low and pte_high, but we are
 * guaranteed that pte_low will not have the present bit set *unless*
 * it is 'l'. Because get_user_pages_fast() only operates on present ptes
 * we're safe.
 */
static inline pte_t gup_get_pte(pte_t *ptep)
{
	pte_t pte;

do {
		pte.pte_low = ptep->pte_low;
		smp_rmb();
		pte.pte_high = ptep->pte_high;
		smp_rmb();
	} while (unlikely(pte.pte_low != ptep->pte_low));

return pte;
}

#include <asm/pgtable-invert.h>

#endif /* _ASM_X86_PGTABLE_3LEVEL_H */