OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 Kbuild	294 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 a.out-core.h	1.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 acenv.h	1.56 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 acpi.h	4.76 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 agp.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 alternative-asm.h	2.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 alternative.h	8.28 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 amd_nb.h	2.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 apb_timer.h	1.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 apic.h	14.53 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 apic_flat_64.h	151 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 apicdef.h	11.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 apm.h	1.8 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 arch_hweight.h	1.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 archrandom.h	3.03 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	946 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm.h	4.97 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 atomic.h	6.02 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 atomic64_32.h	8.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic64_64.h	6.31 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 barrier.h	3.6 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bios_ebda.h	914 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	13.78 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 boot.h	1.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bootparam_utils.h	2.86 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bug.h	2.07 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bugs.h	493 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	641 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	306 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheinfo.h	209 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 calgary.h	2.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ce4100.h	121 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	133 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum_32.h	4.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum_64.h	5.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clocksource.h	488 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmdline.h	302 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	7.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg_32.h	3.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg_64.h	543 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat.h	7.37 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpu.h	975 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu_device_id.h	1.38 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpu_entry_area.h	2.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpufeature.h	7.75 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpufeatures.h	24.62 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpumask.h	408 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 crash.h	320 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📁 crypto	-	11/17/2022 06:42:22 AM	rwxr-xr-x
📄 current.h	443 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 debugreg.h	2.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	208 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 desc.h	11.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 desc_defs.h	3.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 device.h	568 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 disabled-features.h	2.31 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 div64.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	2.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	9.58 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 dmi.h	556 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 dwarf2.h	2.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 e820	-	11/17/2022 06:42:22 AM	rwxr-xr-x
📄 edac.h	474 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 efi.h	6.9 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 elf.h	10.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 emergency-restart.h	202 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 entry_arch.h	1.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 espfix.h	426 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 exec.h	37 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 export.h	120 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable.h	1.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	540 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	6.04 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 floppy.h	6.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 fpu	-	11/17/2022 06:42:22 AM	rwxr-xr-x
📄 frame.h	815 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	1.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gart.h	2.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 genapic.h	22 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 geode.h	842 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	2.3 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 highmem.h	2.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hpet.h	3.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_breakpoint.h	1.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	3.85 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hypervisor.h	1.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i8259.h	1.93 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ia32.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ia32_unistd.h	313 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 imr.h	1.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 inat.h	6.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 inat_types.h	1013 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 init.h	632 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 insn-eval.h	837 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 insn.h	7.46 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 inst.h	5.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel-family.h	3.29 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 intel-mid.h	4.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_ds.h	793 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_mid_vrtc.h	326 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_pmc_ipc.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_pt.h	292 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_punit_ipc.h	4.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_rdt_sched.h	2.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_scu_ipc.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_telemetry.h	3.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 invpcid.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	12.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io_apic.h	5.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 iomap.h	1.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 iommu.h	392 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 iommu_table.h	3.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 iosf_mbi.h	5.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ipi.h	2.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_regs.h	679 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_remapping.h	2.96 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 irq_vectors.h	4.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_work.h	397 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqdomain.h	1.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	4.38 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ist.h	735 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	2.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kasan.h	966 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kaslr.h	424 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kbdleds.h	454 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug.h	752 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec-bzimage64.h	189 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	6.69 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kgdb.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	289 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	3.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_emulate.h	15.23 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_guest.h	172 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_host.h	42.72 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_page_track.h	2.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_para.h	3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvmclock.h	170 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	581 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 livepatch.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 local.h	3.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 local64.h	33 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mach_timer.h	1.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mach_traps.h	1013 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 math_emu.h	395 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc.h	2.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mce.h	12.54 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mem_encrypt.h	2.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 microcode.h	4.14 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 microcode_amd.h	1.41 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 microcode_intel.h	2.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 misc.h	143 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmconfig.h	374 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	10.27 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mmx.h	337 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone.h	129 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone_32.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone_64.h	430 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	2.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpspec.h	3.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpspec_def.h	3.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpx.h	2.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mshyperv.h	10.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msi.h	392 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 msidef.h	1.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msr-index.h	30.36 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 msr-trace.h	1.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msr.h	10.85 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mtrr.h	4.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mwait.h	3.74 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 nmi.h	1.39 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 nops.h	4.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nospec-branch.h	10.87 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 numa.h	2.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 numa_32.h	256 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 numachip	-	11/17/2022 06:42:22 AM	rwxr-xr-x
📄 olpc.h	3.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 olpc_ofw.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 orc_lookup.h	1.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 orc_types.h	3.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	2.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_32.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_32_types.h	1.7 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 page_64.h	1.42 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 page_64_types.h	2.34 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 page_types.h	2.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 paravirt.h	23.31 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 paravirt_types.h	22.15 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 parport.h	314 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pat.h	768 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 pci-direct.h	995 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 pci-functions.h	654 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	3.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci_64.h	684 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci_x86.h	5.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu.h	18.97 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 perf_event.h	8.82 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 perf_event_p4.h	26.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	5.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-2level.h	2.75 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable-2level_types.h	867 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable-3level.h	10.24 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable-3level_types.h	1.06 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable-invert.h	1.07 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable.h	33.91 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable_32.h	3.1 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable_32_types.h	2.01 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable_64.h	7.37 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable_64_types.h	3.67 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable_types.h	16.75 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pkeys.h	3.17 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 platform_sst_audio.h	3.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm-trace.h	611 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 posix_types.h	144 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 preempt.h	3.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 probe_roms.h	273 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor-cyrix.h	879 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor-flags.h	1.71 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 processor.h	24.54 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 prom.h	1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 proto.h	1003 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 pti.h	369 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 ptrace.h	8.52 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 purgatory.h	571 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pvclock-abi.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pvclock.h	2.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 qrwlock.h	199 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 qspinlock.h	2.54 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 qspinlock_paravirt.h	1.85 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 realmode.h	1.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reboot.h	850 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 reboot_fixups.h	183 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 refcount.h	2.83 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 required-features.h	2.81 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 rio.h	2.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rmwcc.h	1.62 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 rwsem.h	7.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
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Editing: bitops.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_BITOPS_H
#define _ASM_X86_BITOPS_H

/*
 * Copyright 1992, Linus Torvalds.
 *
 * Note: inlines with more than a single statement should be marked
 * __always_inline to avoid problems with older gcc's inlining heuristics.
 */

#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif

#include <linux/compiler.h>
#include <asm/alternative.h>
#include <asm/rmwcc.h>
#include <asm/barrier.h>

#if BITS_PER_LONG == 32
# define _BITOPS_LONG_SHIFT 5
#elif BITS_PER_LONG == 64
# define _BITOPS_LONG_SHIFT 6
#else
# error "Unexpected BITS_PER_LONG"
#endif

#define BIT_64(n)			(U64_C(1) << (n))

/*
 * These have to be done with inline assembly: that way the bit-setting
 * is guaranteed to be atomic. All bit operations return 0 if the bit
 * was cleared before the operation and != 0 if it was not.
 *
 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
 */

#define BITOP_ADDR(x) "+m" (*(volatile long *) (x))

#define ADDR				BITOP_ADDR(addr)

/*
 * We do the locked ops that don't return the old value as
 * a mask operation on a byte.
 */
#define IS_IMMEDIATE(nr)		(__builtin_constant_p(nr))
#define CONST_MASK_ADDR(nr, addr)	BITOP_ADDR((void *)(addr) + ((nr)>>3))
#define CONST_MASK(nr)			(1 << ((nr) & 7))

/**
 * set_bit - Atomically set a bit in memory
 * @nr: the bit to set
 * @addr: the address to start counting from
 *
 * This function is atomic and may not be reordered.  See __set_bit()
 * if you do not require the atomic guarantees.
 *
 * Note: there are no guarantees that this function will not be reordered
 * on non x86 architectures, so if you are writing portable code,
 * make sure not to rely on its reordering guarantees.
 *
 * Note that @nr may be almost arbitrarily large; this function is not
 * restricted to acting on a single-word quantity.
 */
static __always_inline void
set_bit(long nr, volatile unsigned long *addr)
{
	if (IS_IMMEDIATE(nr)) {
		asm volatile(LOCK_PREFIX "orb %1,%0"
			: CONST_MASK_ADDR(nr, addr)
			: "iq" ((u8)CONST_MASK(nr))
			: "memory");
	} else {
		asm volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0"
			: BITOP_ADDR(addr) : "Ir" (nr) : "memory");
	}
}

/**
 * __set_bit - Set a bit in memory
 * @nr: the bit to set
 * @addr: the address to start counting from
 *
 * Unlike set_bit(), this function is non-atomic and may be reordered.
 * If it's called on the same region of memory simultaneously, the effect
 * may be that only one operation succeeds.
 */
static __always_inline void __set_bit(long nr, volatile unsigned long *addr)
{
	asm volatile(__ASM_SIZE(bts) " %1,%0" : ADDR : "Ir" (nr) : "memory");
}

/**
 * clear_bit - Clears a bit in memory
 * @nr: Bit to clear
 * @addr: Address to start counting from
 *
 * clear_bit() is atomic and may not be reordered.  However, it does
 * not contain a memory barrier, so if it is used for locking purposes,
 * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()
 * in order to ensure changes are visible on other processors.
 */
static __always_inline void
clear_bit(long nr, volatile unsigned long *addr)
{
	if (IS_IMMEDIATE(nr)) {
		asm volatile(LOCK_PREFIX "andb %1,%0"
			: CONST_MASK_ADDR(nr, addr)
			: "iq" ((u8)~CONST_MASK(nr)));
	} else {
		asm volatile(LOCK_PREFIX __ASM_SIZE(btr) " %1,%0"
			: BITOP_ADDR(addr)
			: "Ir" (nr));
	}
}

/*
 * clear_bit_unlock - Clears a bit in memory
 * @nr: Bit to clear
 * @addr: Address to start counting from
 *
 * clear_bit() is atomic and implies release semantics before the memory
 * operation. It can be used for an unlock.
 */
static __always_inline void clear_bit_unlock(long nr, volatile unsigned long *addr)
{
	barrier();
	clear_bit(nr, addr);
}

static __always_inline void __clear_bit(long nr, volatile unsigned long *addr)
{
	asm volatile(__ASM_SIZE(btr) " %1,%0" : ADDR : "Ir" (nr));
}

static __always_inline bool clear_bit_unlock_is_negative_byte(long nr, volatile unsigned long *addr)
{
	bool negative;
	asm volatile(LOCK_PREFIX "andb %2,%1"
		CC_SET(s)
		: CC_OUT(s) (negative), ADDR
		: "ir" ((char) ~(1 << nr)) : "memory");
	return negative;
}

// Let everybody know we have it
#define clear_bit_unlock_is_negative_byte clear_bit_unlock_is_negative_byte

/*
 * __clear_bit_unlock - Clears a bit in memory
 * @nr: Bit to clear
 * @addr: Address to start counting from
 *
 * __clear_bit() is non-atomic and implies release semantics before the memory
 * operation. It can be used for an unlock if no other CPUs can concurrently
 * modify other bits in the word.
 *
 * No memory barrier is required here, because x86 cannot reorder stores past
 * older loads. Same principle as spin_unlock.
 */
static __always_inline void __clear_bit_unlock(long nr, volatile unsigned long *addr)
{
	barrier();
	__clear_bit(nr, addr);
}

/**
 * __change_bit - Toggle a bit in memory
 * @nr: the bit to change
 * @addr: the address to start counting from
 *
 * Unlike change_bit(), this function is non-atomic and may be reordered.
 * If it's called on the same region of memory simultaneously, the effect
 * may be that only one operation succeeds.
 */
static __always_inline void __change_bit(long nr, volatile unsigned long *addr)
{
	asm volatile(__ASM_SIZE(btc) " %1,%0" : ADDR : "Ir" (nr));
}

/**
 * change_bit - Toggle a bit in memory
 * @nr: Bit to change
 * @addr: Address to start counting from
 *
 * change_bit() is atomic and may not be reordered.
 * Note that @nr may be almost arbitrarily large; this function is not
 * restricted to acting on a single-word quantity.
 */
static __always_inline void change_bit(long nr, volatile unsigned long *addr)
{
	if (IS_IMMEDIATE(nr)) {
		asm volatile(LOCK_PREFIX "xorb %1,%0"
			: CONST_MASK_ADDR(nr, addr)
			: "iq" ((u8)CONST_MASK(nr)));
	} else {
		asm volatile(LOCK_PREFIX __ASM_SIZE(btc) " %1,%0"
			: BITOP_ADDR(addr)
			: "Ir" (nr));
	}
}

/**
 * test_and_set_bit - Set a bit and return its old value
 * @nr: Bit to set
 * @addr: Address to count from
 *
 * This operation is atomic and cannot be reordered.
 * It also implies a memory barrier.
 */
static __always_inline bool test_and_set_bit(long nr, volatile unsigned long *addr)
{
	GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(bts),
	                 *addr, "Ir", nr, "%0", c);
}

/**
 * test_and_set_bit_lock - Set a bit and return its old value for lock
 * @nr: Bit to set
 * @addr: Address to count from
 *
 * This is the same as test_and_set_bit on x86.
 */
static __always_inline bool
test_and_set_bit_lock(long nr, volatile unsigned long *addr)
{
	return test_and_set_bit(nr, addr);
}

/**
 * __test_and_set_bit - Set a bit and return its old value
 * @nr: Bit to set
 * @addr: Address to count from
 *
 * This operation is non-atomic and can be reordered.
 * If two examples of this operation race, one can appear to succeed
 * but actually fail.  You must protect multiple accesses with a lock.
 */
static __always_inline bool __test_and_set_bit(long nr, volatile unsigned long *addr)
{
	bool oldbit;

asm(__ASM_SIZE(bts) " %2,%1"
	    CC_SET(c)
	    : CC_OUT(c) (oldbit), ADDR
	    : "Ir" (nr));
	return oldbit;
}

/**
 * test_and_clear_bit - Clear a bit and return its old value
 * @nr: Bit to clear
 * @addr: Address to count from
 *
 * This operation is atomic and cannot be reordered.
 * It also implies a memory barrier.
 */
static __always_inline bool test_and_clear_bit(long nr, volatile unsigned long *addr)
{
	GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btr),
	                 *addr, "Ir", nr, "%0", c);
}

/**
 * __test_and_clear_bit - Clear a bit and return its old value
 * @nr: Bit to clear
 * @addr: Address to count from
 *
 * This operation is non-atomic and can be reordered.
 * If two examples of this operation race, one can appear to succeed
 * but actually fail.  You must protect multiple accesses with a lock.
 *
 * Note: the operation is performed atomically with respect to
 * the local CPU, but not other CPUs. Portable code should not
 * rely on this behaviour.
 * KVM relies on this behaviour on x86 for modifying memory that is also
 * accessed from a hypervisor on the same CPU if running in a VM: don't change
 * this without also updating arch/x86/kernel/kvm.c
 */
static __always_inline bool __test_and_clear_bit(long nr, volatile unsigned long *addr)
{
	bool oldbit;

asm volatile(__ASM_SIZE(btr) " %2,%1"
		     CC_SET(c)
		     : CC_OUT(c) (oldbit), ADDR
		     : "Ir" (nr));
	return oldbit;
}

/* WARNING: non atomic and it can be reordered! */
static __always_inline bool __test_and_change_bit(long nr, volatile unsigned long *addr)
{
	bool oldbit;

asm volatile(__ASM_SIZE(btc) " %2,%1"
		     CC_SET(c)
		     : CC_OUT(c) (oldbit), ADDR
		     : "Ir" (nr) : "memory");

return oldbit;
}

/**
 * test_and_change_bit - Change a bit and return its old value
 * @nr: Bit to change
 * @addr: Address to count from
 *
 * This operation is atomic and cannot be reordered.
 * It also implies a memory barrier.
 */
static __always_inline bool test_and_change_bit(long nr, volatile unsigned long *addr)
{
	GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btc),
	                 *addr, "Ir", nr, "%0", c);
}

static __always_inline bool constant_test_bit(long nr, const volatile unsigned long *addr)
{
	return ((1UL << (nr & (BITS_PER_LONG-1))) &
		(addr[nr >> _BITOPS_LONG_SHIFT])) != 0;
}

static __always_inline bool variable_test_bit(long nr, volatile const unsigned long *addr)
{
	bool oldbit;

asm volatile(__ASM_SIZE(bt) " %2,%1"
		     CC_SET(c)
		     : CC_OUT(c) (oldbit)
		     : "m" (*(unsigned long *)addr), "Ir" (nr));

return oldbit;
}

#if 0 /* Fool kernel-doc since it doesn't do macros yet */
/**
 * test_bit - Determine whether a bit is set
 * @nr: bit number to test
 * @addr: Address to start counting from
 */
static bool test_bit(int nr, const volatile unsigned long *addr);
#endif

#define test_bit(nr, addr)			\
	(__builtin_constant_p((nr))		\
	 ? constant_test_bit((nr), (addr))	\
	 : variable_test_bit((nr), (addr)))

/**
 * __ffs - find first set bit in word
 * @word: The word to search
 *
 * Undefined if no bit exists, so code should check against 0 first.
 */
static __always_inline unsigned long __ffs(unsigned long word)
{
	asm("rep; bsf %1,%0"
		: "=r" (word)
		: "rm" (word));
	return word;
}

/**
 * ffz - find first zero bit in word
 * @word: The word to search
 *
 * Undefined if no zero exists, so code should check against ~0UL first.
 */
static __always_inline unsigned long ffz(unsigned long word)
{
	asm("rep; bsf %1,%0"
		: "=r" (word)
		: "r" (~word));
	return word;
}

/*
 * __fls: find last set bit in word
 * @word: The word to search
 *
 * Undefined if no set bit exists, so code should check against 0 first.
 */
static __always_inline unsigned long __fls(unsigned long word)
{
	asm("bsr %1,%0"
	    : "=r" (word)
	    : "rm" (word));
	return word;
}

#undef ADDR

#ifdef __KERNEL__
/**
 * ffs - find first set bit in word
 * @x: the word to search
 *
 * This is defined the same way as the libc and compiler builtin ffs
 * routines, therefore differs in spirit from the other bitops.
 *
 * ffs(value) returns 0 if value is 0 or the position of the first
 * set bit if value is nonzero. The first (least significant) bit
 * is at position 1.
 */
static __always_inline int ffs(int x)
{
	int r;

#ifdef CONFIG_X86_64
	/*
	 * AMD64 says BSFL won't clobber the dest reg if x==0; Intel64 says the
	 * dest reg is undefined if x==0, but their CPU architect says its
	 * value is written to set it to the same as before, except that the
	 * top 32 bits will be cleared.
	 *
	 * We cannot do this on 32 bits because at the very least some
	 * 486 CPUs did not behave this way.
	 */
	asm("bsfl %1,%0"
	    : "=r" (r)
	    : "rm" (x), "0" (-1));
#elif defined(CONFIG_X86_CMOV)
	asm("bsfl %1,%0\n\t"
	    "cmovzl %2,%0"
	    : "=&r" (r) : "rm" (x), "r" (-1));
#else
	asm("bsfl %1,%0\n\t"
	    "jnz 1f\n\t"
	    "movl $-1,%0\n"
	    "1:" : "=r" (r) : "rm" (x));
#endif
	return r + 1;
}

/**
 * fls - find last set bit in word
 * @x: the word to search
 *
 * This is defined in a similar way as the libc and compiler builtin
 * ffs, but returns the position of the most significant set bit.
 *
 * fls(value) returns 0 if value is 0 or the position of the last
 * set bit if value is nonzero. The last (most significant) bit is
 * at position 32.
 */
static __always_inline int fls(int x)
{
	int r;

#ifdef CONFIG_X86_64
	/*
	 * AMD64 says BSRL won't clobber the dest reg if x==0; Intel64 says the
	 * dest reg is undefined if x==0, but their CPU architect says its
	 * value is written to set it to the same as before, except that the
	 * top 32 bits will be cleared.
	 *
	 * We cannot do this on 32 bits because at the very least some
	 * 486 CPUs did not behave this way.
	 */
	asm("bsrl %1,%0"
	    : "=r" (r)
	    : "rm" (x), "0" (-1));
#elif defined(CONFIG_X86_CMOV)
	asm("bsrl %1,%0\n\t"
	    "cmovzl %2,%0"
	    : "=&r" (r) : "rm" (x), "rm" (-1));
#else
	asm("bsrl %1,%0\n\t"
	    "jnz 1f\n\t"
	    "movl $-1,%0\n"
	    "1:" : "=r" (r) : "rm" (x));
#endif
	return r + 1;
}

/**
 * fls64 - find last set bit in a 64-bit word
 * @x: the word to search
 *
 * This is defined in a similar way as the libc and compiler builtin
 * ffsll, but returns the position of the most significant set bit.
 *
 * fls64(value) returns 0 if value is 0 or the position of the last
 * set bit if value is nonzero. The last (most significant) bit is
 * at position 64.
 */
#ifdef CONFIG_X86_64
static __always_inline int fls64(__u64 x)
{
	int bitpos = -1;
	/*
	 * AMD64 says BSRQ won't clobber the dest reg if x==0; Intel64 says the
	 * dest reg is undefined if x==0, but their CPU architect says its
	 * value is written to set it to the same as before.
	 */
	asm("bsrq %1,%q0"
	    : "+r" (bitpos)
	    : "rm" (x));
	return bitpos + 1;
}
#else
#include <asm-generic/bitops/fls64.h>
#endif

#include <asm-generic/bitops/find.h>

#include <asm-generic/bitops/sched.h>

#include <asm/arch_hweight.h>

#include <asm-generic/bitops/const_hweight.h>

#include <asm-generic/bitops/le.h>

#include <asm-generic/bitops/ext2-atomic-setbit.h>

#endif /* __KERNEL__ */
#endif /* _ASM_X86_BITOPS_H */