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linux-headers-4.15.0-197
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11/17/2022 06:42:15 AM
rwxr-xr-x
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Kbuild
577 bytes
01/28/2018 09:20:33 PM
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abi.h
853 bytes
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addrspace.h
4.1 KB
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amon.h
409 bytes
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arch_hweight.h
792 bytes
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asm-eva.h
6.82 KB
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asm-offsets.h
35 bytes
01/28/2018 09:20:33 PM
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asm-prototypes.h
197 bytes
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asm.h
8.47 KB
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asmmacro-32.h
2.47 KB
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asmmacro-64.h
1.22 KB
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asmmacro.h
14.07 KB
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atomic.h
19.73 KB
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barrier.h
8.03 KB
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bcache.h
2.04 KB
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bitops.h
15.46 KB
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bitrev.h
608 bytes
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bmips-spaces.h
268 bytes
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bmips.h
3.45 KB
11/01/2022 04:52:05 PM
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bootinfo.h
5.08 KB
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branch.h
2.35 KB
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break.h
787 bytes
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bug.h
759 bytes
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bugs.h
944 bytes
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cache.h
546 bytes
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cacheflush.h
4.99 KB
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cacheops.h
3.71 KB
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cdmm.h
3.67 KB
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cevt-r4k.h
823 bytes
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checksum.h
6.43 KB
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clock.h
997 bytes
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clocksource.h
884 bytes
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cmp.h
492 bytes
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cmpxchg.h
5.28 KB
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compat-signal.h
640 bytes
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compat.h
6.66 KB
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compiler.h
2.96 KB
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cop2.h
1.77 KB
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cpu-features.h
19.46 KB
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cpu-info.h
5.84 KB
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cpu-type.h
4.13 KB
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cpu.h
15.54 KB
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cpufeature.h
717 bytes
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debug.h
654 bytes
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dec
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11/17/2022 06:42:20 AM
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delay.h
841 bytes
01/28/2018 09:20:33 PM
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device.h
347 bytes
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div64.h
2.17 KB
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dma-coherence.h
813 bytes
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dma-mapping.h
981 bytes
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dma.h
9.92 KB
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ds1287.h
1019 bytes
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dsemul.h
3.24 KB
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dsp.h
1.91 KB
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edac.h
819 bytes
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elf.h
15.04 KB
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emma
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11/17/2022 06:42:20 AM
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errno.h
429 bytes
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eva.h
796 bytes
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exec.h
579 bytes
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extable.h
241 bytes
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fb.h
372 bytes
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fixmap.h
2.29 KB
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floppy.h
1.57 KB
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fpregdef.h
2.66 KB
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fpu.h
5.21 KB
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fpu_emulator.h
5.74 KB
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ftrace.h
2.11 KB
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futex.h
4.87 KB
01/28/2018 09:20:33 PM
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fw
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11/17/2022 06:42:20 AM
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gio_device.h
1.5 KB
01/28/2018 09:20:33 PM
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gt64120.h
19.37 KB
01/28/2018 09:20:33 PM
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hardirq.h
544 bytes
01/28/2018 09:20:33 PM
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hazards.h
8.36 KB
01/28/2018 09:20:33 PM
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highmem.h
1.72 KB
01/28/2018 09:20:33 PM
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hpet.h
1.93 KB
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hugetlb.h
2.76 KB
11/01/2022 04:52:05 PM
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hw_irq.h
475 bytes
01/28/2018 09:20:33 PM
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i8259.h
2.52 KB
01/28/2018 09:20:33 PM
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ide.h
330 bytes
01/28/2018 09:20:33 PM
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idle.h
689 bytes
01/28/2018 09:20:33 PM
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inst.h
2.34 KB
01/28/2018 09:20:33 PM
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io.h
18.44 KB
11/01/2022 04:52:05 PM
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📁
ip32
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11/17/2022 06:42:20 AM
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irq.h
2.26 KB
01/28/2018 09:20:33 PM
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irq_cpu.h
708 bytes
01/28/2018 09:20:33 PM
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irq_gt641xx.h
2.69 KB
01/28/2018 09:20:33 PM
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irq_regs.h
744 bytes
01/28/2018 09:20:33 PM
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irqflags.h
4.04 KB
01/28/2018 09:20:33 PM
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isa-rev.h
556 bytes
11/01/2022 04:52:05 PM
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isadep.h
603 bytes
01/28/2018 09:20:33 PM
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jazz.h
8 KB
01/28/2018 09:20:33 PM
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jazzdma.h
2.97 KB
01/28/2018 09:20:33 PM
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jump_label.h
1.4 KB
11/01/2022 04:52:05 PM
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kdebug.h
303 bytes
01/28/2018 09:20:33 PM
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kexec.h
1.53 KB
11/01/2022 04:52:05 PM
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kgdb.h
1.19 KB
01/28/2018 09:20:33 PM
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kmap_types.h
221 bytes
01/28/2018 09:20:33 PM
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kprobes.h
2.68 KB
01/28/2018 09:20:33 PM
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kvm_host.h
37.88 KB
11/01/2022 04:52:05 PM
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kvm_para.h
2.09 KB
01/28/2018 09:20:33 PM
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📁
lasat
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11/17/2022 06:42:20 AM
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linkage.h
306 bytes
01/28/2018 09:20:33 PM
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llsc.h
623 bytes
01/28/2018 09:20:33 PM
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local.h
4.99 KB
01/28/2018 09:20:33 PM
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m48t37.h
732 bytes
01/28/2018 09:20:33 PM
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maar.h
4.04 KB
01/28/2018 09:20:33 PM
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mach-ar7
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11/17/2022 06:42:20 AM
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mach-ath25
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11/17/2022 06:42:20 AM
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mach-ath79
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11/17/2022 06:42:20 AM
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mach-au1x00
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11/17/2022 06:42:20 AM
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mach-bcm47xx
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11/17/2022 06:42:20 AM
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mach-bcm63xx
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11/17/2022 06:42:20 AM
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mach-bmips
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11/17/2022 06:42:20 AM
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mach-cavium-octeon
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11/17/2022 06:42:20 AM
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mach-cobalt
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mach-db1x00
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11/17/2022 06:42:20 AM
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mach-dec
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mach-emma2rh
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mach-generic
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mach-ip22
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mach-ip27
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mach-ip32
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mach-jazz
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mach-jz4740
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mach-lantiq
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mach-lasat
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mach-loongson32
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11/17/2022 06:42:20 AM
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mach-loongson64
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mach-malta
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11/17/2022 06:42:20 AM
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mach-netlogic
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11/17/2022 06:42:20 AM
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mach-paravirt
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11/17/2022 06:42:20 AM
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mach-pic32
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mach-pistachio
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11/17/2022 06:42:20 AM
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mach-pmcs-msp71xx
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mach-pnx833x
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mach-ralink
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mach-rc32434
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mach-rm
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mach-sibyte
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mach-tx39xx
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mach-tx49xx
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mach-vr41xx
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mach-xilfpga
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machine.h
2.93 KB
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mc146818-time.h
3.69 KB
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mc146818rtc.h
450 bytes
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mips-boards
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mips-cm.h
15.86 KB
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mips-cpc.h
5.83 KB
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mips-cps.h
6.55 KB
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mips-gic.h
12.3 KB
11/01/2022 04:52:05 PM
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mips-r2-to-r6-emul.h
2.05 KB
01/28/2018 09:20:33 PM
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mips_machine.h
1.32 KB
01/28/2018 09:20:33 PM
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mips_mt.h
707 bytes
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mipsmtregs.h
10.9 KB
01/28/2018 09:20:33 PM
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mipsprom.h
2.1 KB
01/28/2018 09:20:33 PM
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mipsregs.h
88.1 KB
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mmu.h
550 bytes
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mmu_context.h
5.41 KB
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mmzone.h
561 bytes
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module.h
4.45 KB
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msa.h
8.01 KB
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msc01_ic.h
6.55 KB
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netlogic
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nile4.h
10.33 KB
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octeon
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paccess.h
3.07 KB
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page.h
7.19 KB
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pci
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pci.h
4.08 KB
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perf_event.h
482 bytes
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pgalloc.h
3.21 KB
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pgtable-32.h
7.31 KB
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pgtable-64.h
10.87 KB
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pgtable-bits.h
7.36 KB
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pgtable.h
17.34 KB
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pm-cps.h
1.68 KB
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pm.h
3.99 KB
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pmon.h
1.64 KB
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prefetch.h
2.1 KB
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processor.h
11.71 KB
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prom.h
845 bytes
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ptrace.h
5.55 KB
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r4k-timer.h
604 bytes
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r4kcache.h
26.34 KB
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reboot.h
440 bytes
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reg.h
26 bytes
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regdef.h
2.63 KB
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rtlx.h
2.1 KB
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seccomp.h
800 bytes
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serial.h
607 bytes
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setup.h
884 bytes
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sgi
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sgialib.h
2.45 KB
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sgiarcs.h
15.32 KB
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shmparam.h
352 bytes
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sibyte
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sigcontext.h
1.04 KB
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signal.h
1.02 KB
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sim.h
2.32 KB
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smp-cps.h
1.18 KB
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smp-ops.h
2.33 KB
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smp.h
3.31 KB
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sn
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sni.h
7.27 KB
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socket.h
1.34 KB
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sparsemem.h
486 bytes
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spinlock.h
459 bytes
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Editing: war.h
Close
/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2002, 2004, 2007 by Ralf Baechle * Copyright (C) 2007 Maciej W. Rozycki */ #ifndef _ASM_WAR_H #define _ASM_WAR_H #include <war.h> /* * Work around certain R4000 CPU errata (as implemented by GCC): * * - A double-word or a variable shift may give an incorrect result * if executed immediately after starting an integer division: * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", * erratum #28 * "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum * #19 * * - A double-word or a variable shift may give an incorrect result * if executed while an integer multiplication is in progress: * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", * errata #16 & #28 * * - An integer division may give an incorrect result if started in * a delay slot of a taken branch or a jump: * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", * erratum #52 */ #ifdef CONFIG_CPU_R4000_WORKAROUNDS #define R4000_WAR 1 #else #define R4000_WAR 0 #endif /* * Work around certain R4400 CPU errata (as implemented by GCC): * * - A double-word or a variable shift may give an incorrect result * if executed immediately after starting an integer division: * "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10 * "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4 */ #ifdef CONFIG_CPU_R4400_WORKAROUNDS #define R4400_WAR 1 #else #define R4400_WAR 0 #endif /* * Work around the "daddi" and "daddiu" CPU errata: * * - The `daddi' instruction fails to trap on overflow. * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", * erratum #23 * * - The `daddiu' instruction can produce an incorrect result. * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", * erratum #41 * "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum * #15 * "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7 * "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5 */ #ifdef CONFIG_CPU_DADDI_WORKAROUNDS #define DADDI_WAR 1 #else #define DADDI_WAR 0 #endif /* * Another R4600 erratum. Due to the lack of errata information the exact * technical details aren't known. I've experimentally found that disabling * interrupts during indexed I-cache flushes seems to be sufficient to deal * with the issue. */ #ifndef R4600_V1_INDEX_ICACHEOP_WAR #error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform #endif /* * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: * * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, * Hit_Invalidate_D and Create_Dirty_Excl_D should only be * executed if there is no other dcache activity. If the dcache is * accessed for another instruction immeidately preceding when these * cache instructions are executing, it is possible that the dcache * tag match outputs used by these cache instructions will be * incorrect. These cache instructions should be preceded by at least * four instructions that are not any kind of load or store * instruction. * * This is not allowed: lw * nop * nop * nop * cache Hit_Writeback_Invalidate_D * * This is allowed: lw * nop * nop * nop * nop * cache Hit_Writeback_Invalidate_D */ #ifndef R4600_V1_HIT_CACHEOP_WAR #error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform #endif /* * Writeback and invalidate the primary cache dcache before DMA. * * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only * operate correctly if the internal data cache refill buffer is empty. These * CACHE instructions should be separated from any potential data cache miss * by a load instruction to an uncached address to empty the response buffer." * (Revision 2.0 device errata from IDT available on http://www.idt.com/ * in .pdf format.) */ #ifndef R4600_V2_HIT_CACHEOP_WAR #error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform #endif /* * When an interrupt happens on a CP0 register read instruction, CPU may * lock up or read corrupted values of CP0 registers after it enters * the exception handler. * * This workaround makes sure that we read a "safe" CP0 register as the * first thing in the exception handler, which breaks one of the * pre-conditions for this problem. */ #ifndef R5432_CP0_INTERRUPT_WAR #error Check setting of R5432_CP0_INTERRUPT_WAR for your platform #endif /* * Workaround for the Sibyte M3 errata the text of which can be found at * * http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt * * This will enable the use of a special TLB refill handler which does a * consistency check on the information in c0_badvaddr and c0_entryhi and * will just return and take the exception again if the information was * found to be inconsistent. */ #ifndef BCM1250_M3_WAR #error Check setting of BCM1250_M3_WAR for your platform #endif /* * This is a DUART workaround related to glitches around register accesses */ #ifndef SIBYTE_1956_WAR #error Check setting of SIBYTE_1956_WAR for your platform #endif /* * Fill buffers not flushed on CACHE instructions * * Hit_Invalidate_I cacheops invalidate an icache line but the refill * for that line can get stale data from the fill buffer instead of * accessing memory if the previous icache miss was also to that line. * * Workaround: generate an icache refill from a different line * * Affects: * MIPS 4K RTL revision <3.0, PRID revision <4 */ #ifndef MIPS4K_ICACHE_REFILL_WAR #error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform #endif /* * Missing implicit forced flush of evictions caused by CACHE * instruction * * Evictions caused by a CACHE instructions are not forced on to the * bus. The BIU gives higher priority to fetches than to the data from * the eviction buffer and no collision detection is performed between * fetches and pending data from the eviction buffer. * * Workaround: Execute a SYNC instruction after the cache instruction * * Affects: * MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8 * MIPS 20Kc RTL revision <4.0, PRID revision <? */ #ifndef MIPS_CACHE_SYNC_WAR #error Check setting of MIPS_CACHE_SYNC_WAR for your platform #endif /* * From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for * the line which this instruction itself exists, the following * operation is not guaranteed." * * Workaround: do two phase flushing for Index_Invalidate_I */ #ifndef TX49XX_ICACHE_INDEX_INV_WAR #error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform #endif /* * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra * opposes it being called that) where invalid instructions in the same * I-cache line worth of instructions being fetched may case spurious * exceptions. */ #ifndef ICACHE_REFILLS_WORKAROUND_WAR #error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform #endif /* * On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that * may cause ll / sc and lld / scd sequences to execute non-atomically. */ #ifndef R10000_LLSC_WAR #error Check setting of R10000_LLSC_WAR for your platform #endif /* * 34K core erratum: "Problems Executing the TLBR Instruction" */ #ifndef MIPS34K_MISSED_ITLB_WAR #error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform #endif #endif /* _ASM_WAR_H */