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linux-headers-4.15.0-197
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11/17/2022 06:42:15 AM
rwxr-xr-x
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Kbuild
577 bytes
01/28/2018 09:20:33 PM
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abi.h
853 bytes
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addrspace.h
4.1 KB
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amon.h
409 bytes
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arch_hweight.h
792 bytes
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asm-eva.h
6.82 KB
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asm-offsets.h
35 bytes
01/28/2018 09:20:33 PM
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asm-prototypes.h
197 bytes
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asm.h
8.47 KB
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asmmacro-32.h
2.47 KB
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asmmacro-64.h
1.22 KB
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asmmacro.h
14.07 KB
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atomic.h
19.73 KB
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barrier.h
8.03 KB
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bcache.h
2.04 KB
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bitops.h
15.46 KB
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bitrev.h
608 bytes
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bmips-spaces.h
268 bytes
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bmips.h
3.45 KB
11/01/2022 04:52:05 PM
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bootinfo.h
5.08 KB
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branch.h
2.35 KB
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break.h
787 bytes
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bug.h
759 bytes
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bugs.h
944 bytes
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cache.h
546 bytes
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cacheflush.h
4.99 KB
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cacheops.h
3.71 KB
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cdmm.h
3.67 KB
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cevt-r4k.h
823 bytes
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checksum.h
6.43 KB
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clock.h
997 bytes
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clocksource.h
884 bytes
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cmp.h
492 bytes
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cmpxchg.h
5.28 KB
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compat-signal.h
640 bytes
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compat.h
6.66 KB
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compiler.h
2.96 KB
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cop2.h
1.77 KB
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cpu-features.h
19.46 KB
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cpu-info.h
5.84 KB
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cpu-type.h
4.13 KB
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cpu.h
15.54 KB
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cpufeature.h
717 bytes
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debug.h
654 bytes
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dec
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11/17/2022 06:42:20 AM
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delay.h
841 bytes
01/28/2018 09:20:33 PM
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device.h
347 bytes
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div64.h
2.17 KB
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dma-coherence.h
813 bytes
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dma-mapping.h
981 bytes
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dma.h
9.92 KB
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ds1287.h
1019 bytes
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dsemul.h
3.24 KB
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dsp.h
1.91 KB
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edac.h
819 bytes
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elf.h
15.04 KB
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emma
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11/17/2022 06:42:20 AM
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errno.h
429 bytes
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eva.h
796 bytes
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exec.h
579 bytes
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extable.h
241 bytes
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fb.h
372 bytes
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fixmap.h
2.29 KB
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floppy.h
1.57 KB
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fpregdef.h
2.66 KB
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fpu.h
5.21 KB
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fpu_emulator.h
5.74 KB
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ftrace.h
2.11 KB
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futex.h
4.87 KB
01/28/2018 09:20:33 PM
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fw
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11/17/2022 06:42:20 AM
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gio_device.h
1.5 KB
01/28/2018 09:20:33 PM
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gt64120.h
19.37 KB
01/28/2018 09:20:33 PM
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hardirq.h
544 bytes
01/28/2018 09:20:33 PM
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hazards.h
8.36 KB
01/28/2018 09:20:33 PM
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highmem.h
1.72 KB
01/28/2018 09:20:33 PM
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hpet.h
1.93 KB
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hugetlb.h
2.76 KB
11/01/2022 04:52:05 PM
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hw_irq.h
475 bytes
01/28/2018 09:20:33 PM
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i8259.h
2.52 KB
01/28/2018 09:20:33 PM
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ide.h
330 bytes
01/28/2018 09:20:33 PM
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idle.h
689 bytes
01/28/2018 09:20:33 PM
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inst.h
2.34 KB
01/28/2018 09:20:33 PM
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io.h
18.44 KB
11/01/2022 04:52:05 PM
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📁
ip32
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11/17/2022 06:42:20 AM
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irq.h
2.26 KB
01/28/2018 09:20:33 PM
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irq_cpu.h
708 bytes
01/28/2018 09:20:33 PM
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irq_gt641xx.h
2.69 KB
01/28/2018 09:20:33 PM
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irq_regs.h
744 bytes
01/28/2018 09:20:33 PM
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irqflags.h
4.04 KB
01/28/2018 09:20:33 PM
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isa-rev.h
556 bytes
11/01/2022 04:52:05 PM
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isadep.h
603 bytes
01/28/2018 09:20:33 PM
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jazz.h
8 KB
01/28/2018 09:20:33 PM
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jazzdma.h
2.97 KB
01/28/2018 09:20:33 PM
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jump_label.h
1.4 KB
11/01/2022 04:52:05 PM
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kdebug.h
303 bytes
01/28/2018 09:20:33 PM
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kexec.h
1.53 KB
11/01/2022 04:52:05 PM
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kgdb.h
1.19 KB
01/28/2018 09:20:33 PM
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kmap_types.h
221 bytes
01/28/2018 09:20:33 PM
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kprobes.h
2.68 KB
01/28/2018 09:20:33 PM
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kvm_host.h
37.88 KB
11/01/2022 04:52:05 PM
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kvm_para.h
2.09 KB
01/28/2018 09:20:33 PM
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📁
lasat
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11/17/2022 06:42:20 AM
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linkage.h
306 bytes
01/28/2018 09:20:33 PM
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llsc.h
623 bytes
01/28/2018 09:20:33 PM
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local.h
4.99 KB
01/28/2018 09:20:33 PM
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m48t37.h
732 bytes
01/28/2018 09:20:33 PM
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maar.h
4.04 KB
01/28/2018 09:20:33 PM
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mach-ar7
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11/17/2022 06:42:20 AM
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mach-ath25
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11/17/2022 06:42:20 AM
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mach-ath79
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11/17/2022 06:42:20 AM
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mach-au1x00
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11/17/2022 06:42:20 AM
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mach-bcm47xx
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11/17/2022 06:42:20 AM
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mach-bcm63xx
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11/17/2022 06:42:20 AM
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mach-bmips
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11/17/2022 06:42:20 AM
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mach-cavium-octeon
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11/17/2022 06:42:20 AM
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mach-cobalt
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mach-db1x00
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11/17/2022 06:42:20 AM
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mach-dec
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mach-emma2rh
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mach-generic
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mach-ip22
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mach-ip27
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mach-ip32
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mach-jazz
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mach-jz4740
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mach-lantiq
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mach-lasat
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mach-loongson32
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11/17/2022 06:42:20 AM
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mach-loongson64
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mach-malta
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11/17/2022 06:42:20 AM
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mach-netlogic
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11/17/2022 06:42:20 AM
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mach-paravirt
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11/17/2022 06:42:20 AM
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mach-pic32
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mach-pistachio
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11/17/2022 06:42:20 AM
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mach-pmcs-msp71xx
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mach-pnx833x
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mach-ralink
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mach-rc32434
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mach-rm
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mach-sibyte
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mach-tx39xx
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mach-tx49xx
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mach-vr41xx
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mach-xilfpga
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machine.h
2.93 KB
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mc146818-time.h
3.69 KB
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mc146818rtc.h
450 bytes
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mips-boards
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mips-cm.h
15.86 KB
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mips-cpc.h
5.83 KB
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mips-cps.h
6.55 KB
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mips-gic.h
12.3 KB
11/01/2022 04:52:05 PM
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mips-r2-to-r6-emul.h
2.05 KB
01/28/2018 09:20:33 PM
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mips_machine.h
1.32 KB
01/28/2018 09:20:33 PM
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mips_mt.h
707 bytes
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mipsmtregs.h
10.9 KB
01/28/2018 09:20:33 PM
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mipsprom.h
2.1 KB
01/28/2018 09:20:33 PM
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mipsregs.h
88.1 KB
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mmu.h
550 bytes
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mmu_context.h
5.41 KB
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mmzone.h
561 bytes
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module.h
4.45 KB
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msa.h
8.01 KB
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msc01_ic.h
6.55 KB
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netlogic
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nile4.h
10.33 KB
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octeon
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paccess.h
3.07 KB
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page.h
7.19 KB
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pci
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pci.h
4.08 KB
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perf_event.h
482 bytes
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pgalloc.h
3.21 KB
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pgtable-32.h
7.31 KB
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pgtable-64.h
10.87 KB
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pgtable-bits.h
7.36 KB
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pgtable.h
17.34 KB
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pm-cps.h
1.68 KB
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pm.h
3.99 KB
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pmon.h
1.64 KB
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prefetch.h
2.1 KB
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processor.h
11.71 KB
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prom.h
845 bytes
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ptrace.h
5.55 KB
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r4k-timer.h
604 bytes
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r4kcache.h
26.34 KB
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reboot.h
440 bytes
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reg.h
26 bytes
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regdef.h
2.63 KB
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rtlx.h
2.1 KB
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seccomp.h
800 bytes
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serial.h
607 bytes
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setup.h
884 bytes
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sgi
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sgialib.h
2.45 KB
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sgiarcs.h
15.32 KB
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shmparam.h
352 bytes
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sibyte
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sigcontext.h
1.04 KB
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signal.h
1.02 KB
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sim.h
2.32 KB
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smp-cps.h
1.18 KB
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smp-ops.h
2.33 KB
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smp.h
3.31 KB
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sn
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sni.h
7.27 KB
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socket.h
1.34 KB
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sparsemem.h
486 bytes
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spinlock.h
459 bytes
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Editing: asm.h
Close
/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle * Copyright (C) 1999 by Silicon Graphics, Inc. * Copyright (C) 2001 MIPS Technologies, Inc. * Copyright (C) 2002 Maciej W. Rozycki * * Some useful macros for MIPS assembler code * * Some of the routines below contain useless nops that will be optimized * away by gas in -O mode. These nops are however required to fill delay * slots in noreorder mode. */ #ifndef __ASM_ASM_H #define __ASM_ASM_H #include <asm/sgidefs.h> #include <asm/asm-eva.h> #ifndef CAT #ifdef __STDC__ #define __CAT(str1, str2) str1##str2 #else #define __CAT(str1, str2) str1/**/str2 #endif #define CAT(str1, str2) __CAT(str1, str2) #endif /* * PIC specific declarations * Not used for the kernel but here seems to be the right place. */ #ifdef __PIC__ #define CPRESTORE(register) \ .cprestore register #define CPADD(register) \ .cpadd register #define CPLOAD(register) \ .cpload register #else #define CPRESTORE(register) #define CPADD(register) #define CPLOAD(register) #endif /* * LEAF - declare leaf routine */ #define LEAF(symbol) \ .globl symbol; \ .align 2; \ .type symbol, @function; \ .ent symbol, 0; \ symbol: .frame sp, 0, ra; \ .cfi_startproc; \ .insn /* * NESTED - declare nested routine entry point */ #define NESTED(symbol, framesize, rpc) \ .globl symbol; \ .align 2; \ .type symbol, @function; \ .ent symbol, 0; \ symbol: .frame sp, framesize, rpc; \ .cfi_startproc; \ .insn /* * END - mark end of function */ #define END(function) \ .cfi_endproc; \ .end function; \ .size function, .-function /* * EXPORT - export definition of symbol */ #define EXPORT(symbol) \ .globl symbol; \ symbol: /* * FEXPORT - export definition of a function symbol */ #define FEXPORT(symbol) \ .globl symbol; \ .type symbol, @function; \ symbol: .insn /* * ABS - export absolute symbol */ #define ABS(symbol,value) \ .globl symbol; \ symbol = value #define PANIC(msg) \ .set push; \ .set reorder; \ PTR_LA a0, 8f; \ jal panic; \ 9: b 9b; \ .set pop; \ TEXT(msg) /* * Print formatted string */ #ifdef CONFIG_PRINTK #define PRINT(string) \ .set push; \ .set reorder; \ PTR_LA a0, 8f; \ jal printk; \ .set pop; \ TEXT(string) #else #define PRINT(string) #endif #define TEXT(msg) \ .pushsection .data; \ 8: .asciiz msg; \ .popsection; /* * Build text tables */ #define TTABLE(string) \ .pushsection .text; \ .word 1f; \ .popsection \ .pushsection .data; \ 1: .asciiz string; \ .popsection /* * MIPS IV pref instruction. * Use with .set noreorder only! * * MIPS IV implementations are free to treat this as a nop. The R5000 * is one of them. So we should have an option not to use this instruction. */ #ifdef CONFIG_CPU_HAS_PREFETCH #define PREF(hint,addr) \ .set push; \ .set arch=r5000; \ pref hint, addr; \ .set pop #define PREFE(hint, addr) \ .set push; \ .set mips0; \ .set eva; \ prefe hint, addr; \ .set pop #define PREFX(hint,addr) \ .set push; \ .set arch=r5000; \ prefx hint, addr; \ .set pop #else /* !CONFIG_CPU_HAS_PREFETCH */ #define PREF(hint, addr) #define PREFE(hint, addr) #define PREFX(hint, addr) #endif /* !CONFIG_CPU_HAS_PREFETCH */ /* * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. */ #if (_MIPS_ISA == _MIPS_ISA_MIPS1) #define MOVN(rd, rs, rt) \ .set push; \ .set reorder; \ beqz rt, 9f; \ move rd, rs; \ .set pop; \ 9: #define MOVZ(rd, rs, rt) \ .set push; \ .set reorder; \ bnez rt, 9f; \ move rd, rs; \ .set pop; \ 9: #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) #define MOVN(rd, rs, rt) \ .set push; \ .set noreorder; \ bnezl rt, 9f; \ move rd, rs; \ .set pop; \ 9: #define MOVZ(rd, rs, rt) \ .set push; \ .set noreorder; \ beqzl rt, 9f; \ move rd, rs; \ .set pop; \ 9: #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) #define MOVN(rd, rs, rt) \ movn rd, rs, rt #define MOVZ(rd, rs, rt) \ movz rd, rs, rt #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ /* * Stack alignment */ #if (_MIPS_SIM == _MIPS_SIM_ABI32) #define ALSZ 7 #define ALMASK ~7 #endif #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) #define ALSZ 15 #define ALMASK ~15 #endif /* * Macros to handle different pointer/register sizes for 32/64-bit code */ /* * Size of a register */ #ifdef __mips64 #define SZREG 8 #else #define SZREG 4 #endif /* * Use the following macros in assemblercode to load/store registers, * pointers etc. */ #if (_MIPS_SIM == _MIPS_SIM_ABI32) #define REG_S sw #define REG_L lw #define REG_SUBU subu #define REG_ADDU addu #endif #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) #define REG_S sd #define REG_L ld #define REG_SUBU dsubu #define REG_ADDU daddu #endif /* * How to add/sub/load/store/shift C int variables. */ #if (_MIPS_SZINT == 32) #define INT_ADD add #define INT_ADDU addu #define INT_ADDI addi #define INT_ADDIU addiu #define INT_SUB sub #define INT_SUBU subu #define INT_L lw #define INT_S sw #define INT_SLL sll #define INT_SLLV sllv #define INT_SRL srl #define INT_SRLV srlv #define INT_SRA sra #define INT_SRAV srav #endif #if (_MIPS_SZINT == 64) #define INT_ADD dadd #define INT_ADDU daddu #define INT_ADDI daddi #define INT_ADDIU daddiu #define INT_SUB dsub #define INT_SUBU dsubu #define INT_L ld #define INT_S sd #define INT_SLL dsll #define INT_SLLV dsllv #define INT_SRL dsrl #define INT_SRLV dsrlv #define INT_SRA dsra #define INT_SRAV dsrav #endif /* * How to add/sub/load/store/shift C long variables. */ #if (_MIPS_SZLONG == 32) #define LONG_ADD add #define LONG_ADDU addu #define LONG_ADDI addi #define LONG_ADDIU addiu #define LONG_SUB sub #define LONG_SUBU subu #define LONG_L lw #define LONG_S sw #define LONG_SP swp #define LONG_SLL sll #define LONG_SLLV sllv #define LONG_SRL srl #define LONG_SRLV srlv #define LONG_SRA sra #define LONG_SRAV srav #define LONG .word #define LONGSIZE 4 #define LONGMASK 3 #define LONGLOG 2 #endif #if (_MIPS_SZLONG == 64) #define LONG_ADD dadd #define LONG_ADDU daddu #define LONG_ADDI daddi #define LONG_ADDIU daddiu #define LONG_SUB dsub #define LONG_SUBU dsubu #define LONG_L ld #define LONG_S sd #define LONG_SP sdp #define LONG_SLL dsll #define LONG_SLLV dsllv #define LONG_SRL dsrl #define LONG_SRLV dsrlv #define LONG_SRA dsra #define LONG_SRAV dsrav #define LONG .dword #define LONGSIZE 8 #define LONGMASK 7 #define LONGLOG 3 #endif /* * How to add/sub/load/store/shift pointers. */ #if (_MIPS_SZPTR == 32) #define PTR_ADD add #define PTR_ADDU addu #define PTR_ADDI addi #define PTR_ADDIU addiu #define PTR_SUB sub #define PTR_SUBU subu #define PTR_L lw #define PTR_S sw #define PTR_LA la #define PTR_LI li #define PTR_SLL sll #define PTR_SLLV sllv #define PTR_SRL srl #define PTR_SRLV srlv #define PTR_SRA sra #define PTR_SRAV srav #define PTR_SCALESHIFT 2 #define PTR .word #define PTRSIZE 4 #define PTRLOG 2 #endif #if (_MIPS_SZPTR == 64) #define PTR_ADD dadd #define PTR_ADDU daddu #define PTR_ADDI daddi #define PTR_ADDIU daddiu #define PTR_SUB dsub #define PTR_SUBU dsubu #define PTR_L ld #define PTR_S sd #define PTR_LA dla #define PTR_LI dli #define PTR_SLL dsll #define PTR_SLLV dsllv #define PTR_SRL dsrl #define PTR_SRLV dsrlv #define PTR_SRA dsra #define PTR_SRAV dsrav #define PTR_SCALESHIFT 3 #define PTR .dword #define PTRSIZE 8 #define PTRLOG 3 #endif /* * Some cp0 registers were extended to 64bit for MIPS III. */ #if (_MIPS_SIM == _MIPS_SIM_ABI32) #define MFC0 mfc0 #define MTC0 mtc0 #endif #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) #define MFC0 dmfc0 #define MTC0 dmtc0 #endif #define SSNOP sll zero, zero, 1 #ifdef CONFIG_SGI_IP28 /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */ #include <asm/cacheops.h> #define R10KCBARRIER(addr) cache Cache_Barrier, addr; #else #define R10KCBARRIER(addr) #endif #endif /* __ASM_ASM_H */