OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:15 AM	rwxr-xr-x
📄 Kbuild	577 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 abi.h	853 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 addrspace.h	4.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amon.h	409 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 arch_hweight.h	792 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-eva.h	6.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	197 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm.h	8.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro-32.h	2.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro-64.h	1.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro.h	14.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	19.73 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 barrier.h	8.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcache.h	2.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	15.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitrev.h	608 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bmips-spaces.h	268 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bmips.h	3.45 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bootinfo.h	5.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 branch.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 break.h	787 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	759 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	944 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	546 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	4.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheops.h	3.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cdmm.h	3.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cevt-r4k.h	823 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	6.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clock.h	997 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 clocksource.h	884 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmp.h	492 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	5.28 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 compat-signal.h	640 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat.h	6.66 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 compiler.h	2.96 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cop2.h	1.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu-features.h	19.46 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpu-info.h	5.84 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpu-type.h	4.13 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpu.h	15.54 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpufeature.h	717 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 debug.h	654 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 dec	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📄 delay.h	841 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 device.h	347 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 div64.h	2.17 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 dma-coherence.h	813 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	981 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	9.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ds1287.h	1019 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dsemul.h	3.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dsp.h	1.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 edac.h	819 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	15.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 emma	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📄 errno.h	429 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 eva.h	796 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 exec.h	579 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable.h	241 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	372 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpregdef.h	2.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu.h	5.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu_emulator.h	5.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	2.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	4.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 fw	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📄 gio_device.h	1.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gt64120.h	19.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	544 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hazards.h	8.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	1.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hpet.h	1.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb.h	2.76 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hw_irq.h	475 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 i8259.h	2.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	330 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 idle.h	689 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 inst.h	2.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	18.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 ip32	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📄 irq.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_cpu.h	708 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_gt641xx.h	2.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_regs.h	744 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	4.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 isa-rev.h	556 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 isadep.h	603 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 jazz.h	8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jazzdma.h	2.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	1.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kdebug.h	303 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	1.53 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kgdb.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	221 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_host.h	37.88 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_para.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 lasat	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📄 linkage.h	306 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 llsc.h	623 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 local.h	4.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 m48t37.h	732 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 maar.h	4.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 mach-ar7	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-ath25	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-ath79	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-au1x00	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-bcm47xx	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-bcm63xx	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-bmips	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-cavium-octeon	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-cobalt	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-db1x00	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-dec	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-emma2rh	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-generic	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-ip22	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-ip27	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-ip28	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-ip32	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-jazz	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-jz4740	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-lantiq	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-lasat	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-loongson32	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-loongson64	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-malta	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-netlogic	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-paravirt	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-pic32	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-pistachio	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-pmcs-msp71xx	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-pnx833x	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-ralink	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-rc32434	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-rm	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-sibyte	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-tx39xx	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-tx49xx	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-vr41xx	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📁 mach-xilfpga	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📄 machine.h	2.93 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mc146818-time.h	3.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc.h	450 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 mips-boards	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📄 mips-cm.h	15.86 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mips-cpc.h	5.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips-cps.h	6.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips-gic.h	12.3 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mips-r2-to-r6-emul.h	2.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips_machine.h	1.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mips_mt.h	707 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mipsmtregs.h	10.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mipsprom.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mipsregs.h	88.1 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mmu.h	550 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 mmu_context.h	5.41 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mmzone.h	561 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 module.h	4.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msa.h	8.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msc01_ic.h	6.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 netlogic	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📄 nile4.h	10.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 octeon	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📄 paccess.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	7.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 pci	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📄 pci.h	4.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	482 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	3.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-32.h	7.31 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable-64.h	10.87 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable-bits.h	7.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	17.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm-cps.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm.h	3.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmon.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 prefetch.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	11.71 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 prom.h	845 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	5.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 r4k-timer.h	604 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 r4kcache.h	26.34 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 reboot.h	440 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 reg.h	26 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 regdef.h	2.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rtlx.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seccomp.h	800 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	607 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	884 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📁 sgi	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📄 sgialib.h	2.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sgiarcs.h	15.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	352 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 sibyte	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📄 sigcontext.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sim.h	2.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp-cps.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp-ops.h	2.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	3.31 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 sn	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📄 sni.h	7.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 socket.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sparsemem.h	486 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	459 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	188 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spram.h	262 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackframe.h	10.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackprotector.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	2.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	4.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	3.57 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 termios.h	2.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	6.63 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 time.h	2.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	2.87 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tlb.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbdebug.h	403 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbex.h	788 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	1.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbmisc.h	320 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	619 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	1.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 txx9	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📄 txx9irq.h	743 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 txx9pio.h	592 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 txx9tmr.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 types.h	487 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	22.2 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 uasm.h	9.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	1.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uprobes.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	3.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	1.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vpe.h	2.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 vr41xx	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📄 war.h	7.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 watch.h	827 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 wbflush.h	694 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 xtalk	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📄 yamon-dt.h	1.88 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: r4kcache.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Inline assembly cache operations.
 *
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org)
 * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
 */
#ifndef _ASM_R4KCACHE_H
#define _ASM_R4KCACHE_H

#include <linux/stringify.h>

#include <asm/asm.h>
#include <asm/cacheops.h>
#include <asm/compiler.h>
#include <asm/cpu-features.h>
#include <asm/cpu-type.h>
#include <asm/mipsmtregs.h>
#include <asm/mmzone.h>
#include <linux/uaccess.h> /* for uaccess_kernel() */

extern void (*r4k_blast_dcache)(void);
extern void (*r4k_blast_icache)(void);

/*
 * This macro return a properly sign-extended address suitable as base address
 * for indexed cache operations.  Two issues here:
 *
 *  - The MIPS32 and MIPS64 specs permit an implementation to directly derive
 *    the index bits from the virtual address.	This breaks with tradition
 *    set by the R4000.	 To keep unpleasant surprises from happening we pick
 *    an address in KSEG0 / CKSEG0.
 *  - We need a properly sign extended address for 64-bit code.	 To get away
 *    without ifdefs we let the compiler do it by a type cast.
 */
#define INDEX_BASE	CKSEG0

#define cache_op(op,addr)						\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noreorder				\n"	\
	"	.set "MIPS_ISA_ARCH_LEVEL"			\n"	\
	"	cache	%0, %1					\n"	\
	"	.set	pop					\n"	\
	:								\
	: "i" (op), "R" (*(unsigned char *)(addr)))

#ifdef CONFIG_MIPS_MT

#define __iflush_prologue						\
	unsigned long redundance;					\
	extern int mt_n_iflushes;					\
	for (redundance = 0; redundance < mt_n_iflushes; redundance++) {

#define __iflush_epilogue						\
	}

#define __dflush_prologue						\
	unsigned long redundance;					\
	extern int mt_n_dflushes;					\
	for (redundance = 0; redundance < mt_n_dflushes; redundance++) {

#define __dflush_epilogue \
	}

#define __inv_dflush_prologue __dflush_prologue
#define __inv_dflush_epilogue __dflush_epilogue
#define __sflush_prologue {
#define __sflush_epilogue }
#define __inv_sflush_prologue __sflush_prologue
#define __inv_sflush_epilogue __sflush_epilogue

#else /* CONFIG_MIPS_MT */

#define __iflush_prologue {
#define __iflush_epilogue }
#define __dflush_prologue {
#define __dflush_epilogue }
#define __inv_dflush_prologue {
#define __inv_dflush_epilogue }
#define __sflush_prologue {
#define __sflush_epilogue }
#define __inv_sflush_prologue {
#define __inv_sflush_epilogue }

#endif /* CONFIG_MIPS_MT */

static inline void flush_icache_line_indexed(unsigned long addr)
{
	__iflush_prologue
	cache_op(Index_Invalidate_I, addr);
	__iflush_epilogue
}

static inline void flush_dcache_line_indexed(unsigned long addr)
{
	__dflush_prologue
	cache_op(Index_Writeback_Inv_D, addr);
	__dflush_epilogue
}

static inline void flush_scache_line_indexed(unsigned long addr)
{
	cache_op(Index_Writeback_Inv_SD, addr);
}

static inline void flush_icache_line(unsigned long addr)
{
	__iflush_prologue
	switch (boot_cpu_type()) {
	case CPU_LOONGSON2:
		cache_op(Hit_Invalidate_I_Loongson2, addr);
		break;

default:
		cache_op(Hit_Invalidate_I, addr);
		break;
	}
	__iflush_epilogue
}

static inline void flush_dcache_line(unsigned long addr)
{
	__dflush_prologue
	cache_op(Hit_Writeback_Inv_D, addr);
	__dflush_epilogue
}

static inline void invalidate_dcache_line(unsigned long addr)
{
	__dflush_prologue
	cache_op(Hit_Invalidate_D, addr);
	__dflush_epilogue
}

static inline void invalidate_scache_line(unsigned long addr)
{
	cache_op(Hit_Invalidate_SD, addr);
}

static inline void flush_scache_line(unsigned long addr)
{
	cache_op(Hit_Writeback_Inv_SD, addr);
}

#define protected_cache_op(op,addr)				\
({								\
	int __err = 0;						\
	__asm__ __volatile__(					\
	"	.set	push			\n"		\
	"	.set	noreorder		\n"		\
	"	.set "MIPS_ISA_ARCH_LEVEL"	\n"		\
	"1:	cache	%1, (%2)		\n"		\
	"2:	.insn				\n"		\
	"	.set	pop			\n"		\
	"	.section .fixup,\"ax\"		\n"		\
	"3:	li	%0, %3			\n"		\
	"	j	2b			\n"		\
	"	.previous			\n"		\
	"	.section __ex_table,\"a\"	\n"		\
	"	"STR(PTR)" 1b, 3b		\n"		\
	"	.previous"					\
	: "+r" (__err)						\
	: "i" (op), "r" (addr), "i" (-EFAULT));			\
	__err;							\
})

#define protected_cachee_op(op,addr)				\
({								\
	int __err = 0;						\
	__asm__ __volatile__(					\
	"	.set	push			\n"		\
	"	.set	noreorder		\n"		\
	"	.set	mips0			\n"		\
	"	.set	eva			\n"		\
	"1:	cachee	%1, (%2)		\n"		\
	"2:	.insn				\n"		\
	"	.set	pop			\n"		\
	"	.section .fixup,\"ax\"		\n"		\
	"3:	li	%0, %3			\n"		\
	"	j	2b			\n"		\
	"	.previous			\n"		\
	"	.section __ex_table,\"a\"	\n"		\
	"	"STR(PTR)" 1b, 3b		\n"		\
	"	.previous"					\
	: "+r" (__err)						\
	: "i" (op), "r" (addr), "i" (-EFAULT));			\
	__err;							\
})

/*
 * The next two are for badland addresses like signal trampolines.
 */
static inline int protected_flush_icache_line(unsigned long addr)
{
	switch (boot_cpu_type()) {
	case CPU_LOONGSON2:
		return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);

default:
#ifdef CONFIG_EVA
		return protected_cachee_op(Hit_Invalidate_I, addr);
#else
		return protected_cache_op(Hit_Invalidate_I, addr);
#endif
	}
}

/*
 * R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D
 * cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style
 * caches.  We're talking about one cacheline unnecessarily getting invalidated
 * here so the penalty isn't overly hard.
 */
static inline int protected_writeback_dcache_line(unsigned long addr)
{
#ifdef CONFIG_EVA
	return protected_cachee_op(Hit_Writeback_Inv_D, addr);
#else
	return protected_cache_op(Hit_Writeback_Inv_D, addr);
#endif
}

static inline int protected_writeback_scache_line(unsigned long addr)
{
#ifdef CONFIG_EVA
	return protected_cachee_op(Hit_Writeback_Inv_SD, addr);
#else
	return protected_cache_op(Hit_Writeback_Inv_SD, addr);
#endif
}

/*
 * This one is RM7000-specific
 */
static inline void invalidate_tcache_page(unsigned long addr)
{
	cache_op(Page_Invalidate_T, addr);
}

#ifndef CONFIG_CPU_MIPSR6
#define cache16_unroll32(base,op)					\
	__asm__ __volatile__(						\
	"	.set push					\n"	\
	"	.set noreorder					\n"	\
	"	.set mips3					\n"	\
	"	cache %1, 0x000(%0); cache %1, 0x010(%0)	\n"	\
	"	cache %1, 0x020(%0); cache %1, 0x030(%0)	\n"	\
	"	cache %1, 0x040(%0); cache %1, 0x050(%0)	\n"	\
	"	cache %1, 0x060(%0); cache %1, 0x070(%0)	\n"	\
	"	cache %1, 0x080(%0); cache %1, 0x090(%0)	\n"	\
	"	cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)	\n"	\
	"	cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)	\n"	\
	"	cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)	\n"	\
	"	cache %1, 0x100(%0); cache %1, 0x110(%0)	\n"	\
	"	cache %1, 0x120(%0); cache %1, 0x130(%0)	\n"	\
	"	cache %1, 0x140(%0); cache %1, 0x150(%0)	\n"	\
	"	cache %1, 0x160(%0); cache %1, 0x170(%0)	\n"	\
	"	cache %1, 0x180(%0); cache %1, 0x190(%0)	\n"	\
	"	cache %1, 0x1a0(%0); cache %1, 0x1b0(%0)	\n"	\
	"	cache %1, 0x1c0(%0); cache %1, 0x1d0(%0)	\n"	\
	"	cache %1, 0x1e0(%0); cache %1, 0x1f0(%0)	\n"	\
	"	.set pop					\n"	\
		:							\
		: "r" (base),						\
		  "i" (op));

#define cache32_unroll32(base,op)					\
	__asm__ __volatile__(						\
	"	.set push					\n"	\
	"	.set noreorder					\n"	\
	"	.set mips3					\n"	\
	"	cache %1, 0x000(%0); cache %1, 0x020(%0)	\n"	\
	"	cache %1, 0x040(%0); cache %1, 0x060(%0)	\n"	\
	"	cache %1, 0x080(%0); cache %1, 0x0a0(%0)	\n"	\
	"	cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)	\n"	\
	"	cache %1, 0x100(%0); cache %1, 0x120(%0)	\n"	\
	"	cache %1, 0x140(%0); cache %1, 0x160(%0)	\n"	\
	"	cache %1, 0x180(%0); cache %1, 0x1a0(%0)	\n"	\
	"	cache %1, 0x1c0(%0); cache %1, 0x1e0(%0)	\n"	\
	"	cache %1, 0x200(%0); cache %1, 0x220(%0)	\n"	\
	"	cache %1, 0x240(%0); cache %1, 0x260(%0)	\n"	\
	"	cache %1, 0x280(%0); cache %1, 0x2a0(%0)	\n"	\
	"	cache %1, 0x2c0(%0); cache %1, 0x2e0(%0)	\n"	\
	"	cache %1, 0x300(%0); cache %1, 0x320(%0)	\n"	\
	"	cache %1, 0x340(%0); cache %1, 0x360(%0)	\n"	\
	"	cache %1, 0x380(%0); cache %1, 0x3a0(%0)	\n"	\
	"	cache %1, 0x3c0(%0); cache %1, 0x3e0(%0)	\n"	\
	"	.set pop					\n"	\
		:							\
		: "r" (base),						\
		  "i" (op));

#define cache64_unroll32(base,op)					\
	__asm__ __volatile__(						\
	"	.set push					\n"	\
	"	.set noreorder					\n"	\
	"	.set mips3					\n"	\
	"	cache %1, 0x000(%0); cache %1, 0x040(%0)	\n"	\
	"	cache %1, 0x080(%0); cache %1, 0x0c0(%0)	\n"	\
	"	cache %1, 0x100(%0); cache %1, 0x140(%0)	\n"	\
	"	cache %1, 0x180(%0); cache %1, 0x1c0(%0)	\n"	\
	"	cache %1, 0x200(%0); cache %1, 0x240(%0)	\n"	\
	"	cache %1, 0x280(%0); cache %1, 0x2c0(%0)	\n"	\
	"	cache %1, 0x300(%0); cache %1, 0x340(%0)	\n"	\
	"	cache %1, 0x380(%0); cache %1, 0x3c0(%0)	\n"	\
	"	cache %1, 0x400(%0); cache %1, 0x440(%0)	\n"	\
	"	cache %1, 0x480(%0); cache %1, 0x4c0(%0)	\n"	\
	"	cache %1, 0x500(%0); cache %1, 0x540(%0)	\n"	\
	"	cache %1, 0x580(%0); cache %1, 0x5c0(%0)	\n"	\
	"	cache %1, 0x600(%0); cache %1, 0x640(%0)	\n"	\
	"	cache %1, 0x680(%0); cache %1, 0x6c0(%0)	\n"	\
	"	cache %1, 0x700(%0); cache %1, 0x740(%0)	\n"	\
	"	cache %1, 0x780(%0); cache %1, 0x7c0(%0)	\n"	\
	"	.set pop					\n"	\
		:							\
		: "r" (base),						\
		  "i" (op));

#define cache128_unroll32(base,op)					\
	__asm__ __volatile__(						\
	"	.set push					\n"	\
	"	.set noreorder					\n"	\
	"	.set mips3					\n"	\
	"	cache %1, 0x000(%0); cache %1, 0x080(%0)	\n"	\
	"	cache %1, 0x100(%0); cache %1, 0x180(%0)	\n"	\
	"	cache %1, 0x200(%0); cache %1, 0x280(%0)	\n"	\
	"	cache %1, 0x300(%0); cache %1, 0x380(%0)	\n"	\
	"	cache %1, 0x400(%0); cache %1, 0x480(%0)	\n"	\
	"	cache %1, 0x500(%0); cache %1, 0x580(%0)	\n"	\
	"	cache %1, 0x600(%0); cache %1, 0x680(%0)	\n"	\
	"	cache %1, 0x700(%0); cache %1, 0x780(%0)	\n"	\
	"	cache %1, 0x800(%0); cache %1, 0x880(%0)	\n"	\
	"	cache %1, 0x900(%0); cache %1, 0x980(%0)	\n"	\
	"	cache %1, 0xa00(%0); cache %1, 0xa80(%0)	\n"	\
	"	cache %1, 0xb00(%0); cache %1, 0xb80(%0)	\n"	\
	"	cache %1, 0xc00(%0); cache %1, 0xc80(%0)	\n"	\
	"	cache %1, 0xd00(%0); cache %1, 0xd80(%0)	\n"	\
	"	cache %1, 0xe00(%0); cache %1, 0xe80(%0)	\n"	\
	"	cache %1, 0xf00(%0); cache %1, 0xf80(%0)	\n"	\
	"	.set pop					\n"	\
		:							\
		: "r" (base),						\
		  "i" (op));

#else
/*
 * MIPS R6 changed the cache opcode and moved to a 8-bit offset field.
 * This means we now need to increment the base register before we flush
 * more cache lines
 */
#define cache16_unroll32(base,op)				\
	__asm__ __volatile__(					\
	"	.set push\n"					\
	"	.set noreorder\n"				\
	"	.set mips64r6\n"				\
	"	.set noat\n"					\
	"	cache %1, 0x000(%0); cache %1, 0x010(%0)\n"	\
	"	cache %1, 0x020(%0); cache %1, 0x030(%0)\n"	\
	"	cache %1, 0x040(%0); cache %1, 0x050(%0)\n"	\
	"	cache %1, 0x060(%0); cache %1, 0x070(%0)\n"	\
	"	cache %1, 0x080(%0); cache %1, 0x090(%0)\n"	\
	"	cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)\n"	\
	"	cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)\n"	\
	"	cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, %0, 0x100	\n"	\
	"	cache %1, 0x000($1); cache %1, 0x010($1)\n"	\
	"	cache %1, 0x020($1); cache %1, 0x030($1)\n"	\
	"	cache %1, 0x040($1); cache %1, 0x050($1)\n"	\
	"	cache %1, 0x060($1); cache %1, 0x070($1)\n"	\
	"	cache %1, 0x080($1); cache %1, 0x090($1)\n"	\
	"	cache %1, 0x0a0($1); cache %1, 0x0b0($1)\n"	\
	"	cache %1, 0x0c0($1); cache %1, 0x0d0($1)\n"	\
	"	cache %1, 0x0e0($1); cache %1, 0x0f0($1)\n"	\
	"	.set pop\n"					\
		:						\
		: "r" (base),					\
		  "i" (op));

#define cache32_unroll32(base,op)				\
	__asm__ __volatile__(					\
	"	.set push\n"					\
	"	.set noreorder\n"				\
	"	.set mips64r6\n"				\
	"	.set noat\n"					\
	"	cache %1, 0x000(%0); cache %1, 0x020(%0)\n"	\
	"	cache %1, 0x040(%0); cache %1, 0x060(%0)\n"	\
	"	cache %1, 0x080(%0); cache %1, 0x0a0(%0)\n"	\
	"	cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, %0, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x020($1)\n"	\
	"	cache %1, 0x040($1); cache %1, 0x060($1)\n"	\
	"	cache %1, 0x080($1); cache %1, 0x0a0($1)\n"	\
	"	cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x020($1)\n"	\
	"	cache %1, 0x040($1); cache %1, 0x060($1)\n"	\
	"	cache %1, 0x080($1); cache %1, 0x0a0($1)\n"	\
	"	cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100\n"	\
	"	cache %1, 0x000($1); cache %1, 0x020($1)\n"	\
	"	cache %1, 0x040($1); cache %1, 0x060($1)\n"	\
	"	cache %1, 0x080($1); cache %1, 0x0a0($1)\n"	\
	"	cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n"	\
	"	.set pop\n"					\
		:						\
		: "r" (base),					\
		  "i" (op));

#define cache64_unroll32(base,op)				\
	__asm__ __volatile__(					\
	"	.set push\n"					\
	"	.set noreorder\n"				\
	"	.set mips64r6\n"				\
	"	.set noat\n"					\
	"	cache %1, 0x000(%0); cache %1, 0x040(%0)\n"	\
	"	cache %1, 0x080(%0); cache %1, 0x0c0(%0)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, %0, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x040($1)\n"	\
	"	cache %1, 0x080($1); cache %1, 0x0c0($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x040($1)\n"	\
	"	cache %1, 0x080($1); cache %1, 0x0c0($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x040($1)\n"	\
	"	cache %1, 0x080($1); cache %1, 0x0c0($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x040($1)\n"	\
	"	cache %1, 0x080($1); cache %1, 0x0c0($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x040($1)\n"	\
	"	cache %1, 0x080($1); cache %1, 0x0c0($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x040($1)\n"	\
	"	cache %1, 0x080($1); cache %1, 0x0c0($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x040($1)\n"	\
	"	cache %1, 0x080($1); cache %1, 0x0c0($1)\n"	\
	"	.set pop\n"					\
		:						\
		: "r" (base),					\
		  "i" (op));

#define cache128_unroll32(base,op)				\
	__asm__ __volatile__(					\
	"	.set push\n"					\
	"	.set noreorder\n"				\
	"	.set mips64r6\n"				\
	"	.set noat\n"					\
	"	cache %1, 0x000(%0); cache %1, 0x080(%0)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, %0, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x080($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x080($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x080($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x080($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x080($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x080($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x080($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x080($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x080($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x080($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x080($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x080($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x080($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x080($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x080($1)\n"	\
	"	"__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"	\
	"	cache %1, 0x000($1); cache %1, 0x080($1)\n"	\
	"	.set pop\n"					\
		:						\
		: "r" (base),					\
		  "i" (op));
#endif /* CONFIG_CPU_MIPSR6 */

/*
 * Perform the cache operation specified by op using a user mode virtual
 * address while in kernel mode.
 */
#define cache16_unroll32_user(base,op)					\
	__asm__ __volatile__(						\
	"	.set push					\n"	\
	"	.set noreorder					\n"	\
	"	.set mips0					\n"	\
	"	.set eva					\n"	\
	"	cachee %1, 0x000(%0); cachee %1, 0x010(%0)	\n"	\
	"	cachee %1, 0x020(%0); cachee %1, 0x030(%0)	\n"	\
	"	cachee %1, 0x040(%0); cachee %1, 0x050(%0)	\n"	\
	"	cachee %1, 0x060(%0); cachee %1, 0x070(%0)	\n"	\
	"	cachee %1, 0x080(%0); cachee %1, 0x090(%0)	\n"	\
	"	cachee %1, 0x0a0(%0); cachee %1, 0x0b0(%0)	\n"	\
	"	cachee %1, 0x0c0(%0); cachee %1, 0x0d0(%0)	\n"	\
	"	cachee %1, 0x0e0(%0); cachee %1, 0x0f0(%0)	\n"	\
	"	cachee %1, 0x100(%0); cachee %1, 0x110(%0)	\n"	\
	"	cachee %1, 0x120(%0); cachee %1, 0x130(%0)	\n"	\
	"	cachee %1, 0x140(%0); cachee %1, 0x150(%0)	\n"	\
	"	cachee %1, 0x160(%0); cachee %1, 0x170(%0)	\n"	\
	"	cachee %1, 0x180(%0); cachee %1, 0x190(%0)	\n"	\
	"	cachee %1, 0x1a0(%0); cachee %1, 0x1b0(%0)	\n"	\
	"	cachee %1, 0x1c0(%0); cachee %1, 0x1d0(%0)	\n"	\
	"	cachee %1, 0x1e0(%0); cachee %1, 0x1f0(%0)	\n"	\
	"	.set pop					\n"	\
		:							\
		: "r" (base),						\
		  "i" (op));

#define cache32_unroll32_user(base, op)					\
	__asm__ __volatile__(						\
	"	.set push					\n"	\
	"	.set noreorder					\n"	\
	"	.set mips0					\n"	\
	"	.set eva					\n"	\
	"	cachee %1, 0x000(%0); cachee %1, 0x020(%0)	\n"	\
	"	cachee %1, 0x040(%0); cachee %1, 0x060(%0)	\n"	\
	"	cachee %1, 0x080(%0); cachee %1, 0x0a0(%0)	\n"	\
	"	cachee %1, 0x0c0(%0); cachee %1, 0x0e0(%0)	\n"	\
	"	cachee %1, 0x100(%0); cachee %1, 0x120(%0)	\n"	\
	"	cachee %1, 0x140(%0); cachee %1, 0x160(%0)	\n"	\
	"	cachee %1, 0x180(%0); cachee %1, 0x1a0(%0)	\n"	\
	"	cachee %1, 0x1c0(%0); cachee %1, 0x1e0(%0)	\n"	\
	"	cachee %1, 0x200(%0); cachee %1, 0x220(%0)	\n"	\
	"	cachee %1, 0x240(%0); cachee %1, 0x260(%0)	\n"	\
	"	cachee %1, 0x280(%0); cachee %1, 0x2a0(%0)	\n"	\
	"	cachee %1, 0x2c0(%0); cachee %1, 0x2e0(%0)	\n"	\
	"	cachee %1, 0x300(%0); cachee %1, 0x320(%0)	\n"	\
	"	cachee %1, 0x340(%0); cachee %1, 0x360(%0)	\n"	\
	"	cachee %1, 0x380(%0); cachee %1, 0x3a0(%0)	\n"	\
	"	cachee %1, 0x3c0(%0); cachee %1, 0x3e0(%0)	\n"	\
	"	.set pop					\n"	\
		:							\
		: "r" (base),						\
		  "i" (op));

#define cache64_unroll32_user(base, op)					\
	__asm__ __volatile__(						\
	"	.set push					\n"	\
	"	.set noreorder					\n"	\
	"	.set mips0					\n"	\
	"	.set eva					\n"	\
	"	cachee %1, 0x000(%0); cachee %1, 0x040(%0)	\n"	\
	"	cachee %1, 0x080(%0); cachee %1, 0x0c0(%0)	\n"	\
	"	cachee %1, 0x100(%0); cachee %1, 0x140(%0)	\n"	\
	"	cachee %1, 0x180(%0); cachee %1, 0x1c0(%0)	\n"	\
	"	cachee %1, 0x200(%0); cachee %1, 0x240(%0)	\n"	\
	"	cachee %1, 0x280(%0); cachee %1, 0x2c0(%0)	\n"	\
	"	cachee %1, 0x300(%0); cachee %1, 0x340(%0)	\n"	\
	"	cachee %1, 0x380(%0); cachee %1, 0x3c0(%0)	\n"	\
	"	cachee %1, 0x400(%0); cachee %1, 0x440(%0)	\n"	\
	"	cachee %1, 0x480(%0); cachee %1, 0x4c0(%0)	\n"	\
	"	cachee %1, 0x500(%0); cachee %1, 0x540(%0)	\n"	\
	"	cachee %1, 0x580(%0); cachee %1, 0x5c0(%0)	\n"	\
	"	cachee %1, 0x600(%0); cachee %1, 0x640(%0)	\n"	\
	"	cachee %1, 0x680(%0); cachee %1, 0x6c0(%0)	\n"	\
	"	cachee %1, 0x700(%0); cachee %1, 0x740(%0)	\n"	\
	"	cachee %1, 0x780(%0); cachee %1, 0x7c0(%0)	\n"	\
	"	.set pop					\n"	\
		:							\
		: "r" (base),						\
		  "i" (op));

/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra)	\
static inline void extra##blast_##pfx##cache##lsize(void)		\
{									\
	unsigned long start = INDEX_BASE;				\
	unsigned long end = start + current_cpu_data.desc.waysize;	\
	unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;	\
	unsigned long ws_end = current_cpu_data.desc.ways <<		\
			       current_cpu_data.desc.waybit;		\
	unsigned long ws, addr;						\
									\
	__##pfx##flush_prologue						\
									\
	for (ws = 0; ws < ws_end; ws += ws_inc)				\
		for (addr = start; addr < end; addr += lsize * 32)	\
			cache##lsize##_unroll32(addr|ws, indexop);	\
									\
	__##pfx##flush_epilogue						\
}									\
									\
static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \
{									\
	unsigned long start = page;					\
	unsigned long end = page + PAGE_SIZE;				\
									\
	__##pfx##flush_prologue						\
									\
	do {								\
		cache##lsize##_unroll32(start, hitop);			\
		start += lsize * 32;					\
	} while (start < end);						\
									\
	__##pfx##flush_epilogue						\
}									\
									\
static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
{									\
	unsigned long indexmask = current_cpu_data.desc.waysize - 1;	\
	unsigned long start = INDEX_BASE + (page & indexmask);		\
	unsigned long end = start + PAGE_SIZE;				\
	unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;	\
	unsigned long ws_end = current_cpu_data.desc.ways <<		\
			       current_cpu_data.desc.waybit;		\
	unsigned long ws, addr;						\
									\
	__##pfx##flush_prologue						\
									\
	for (ws = 0; ws < ws_end; ws += ws_inc)				\
		for (addr = start; addr < end; addr += lsize * 32)	\
			cache##lsize##_unroll32(addr|ws, indexop);	\
									\
	__##pfx##flush_epilogue						\
}

__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )

__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )

#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
{									\
	unsigned long start = page;					\
	unsigned long end = page + PAGE_SIZE;				\
									\
	__##pfx##flush_prologue						\
									\
	do {								\
		cache##lsize##_unroll32_user(start, hitop);             \
		start += lsize * 32;					\
	} while (start < end);						\
									\
	__##pfx##flush_epilogue						\
}

__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
			 16)
__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
			 32)
__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
			 64)
__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)

/* build blast_xxx_range, protected_blast_xxx_range */
#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra)	\
static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
						    unsigned long end)	\
{									\
	unsigned long lsize = cpu_##desc##_line_size();			\
	unsigned long addr = start & ~(lsize - 1);			\
	unsigned long aend = (end - 1) & ~(lsize - 1);			\
									\
	__##pfx##flush_prologue						\
									\
	while (1) {							\
		prot##cache_op(hitop, addr);				\
		if (addr == aend)					\
			break;						\
		addr += lsize;						\
	}								\
									\
	__##pfx##flush_epilogue						\
}

#ifndef CONFIG_EVA

__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )

#else

#define __BUILD_PROT_BLAST_CACHE_RANGE(pfx, desc, hitop)		\
static inline void protected_blast_##pfx##cache##_range(unsigned long start,\
							unsigned long end) \
{									\
	unsigned long lsize = cpu_##desc##_line_size();			\
	unsigned long addr = start & ~(lsize - 1);			\
	unsigned long aend = (end - 1) & ~(lsize - 1);			\
									\
	__##pfx##flush_prologue						\
									\
	if (!uaccess_kernel()) {					\
		while (1) {						\
			protected_cachee_op(hitop, addr);		\
			if (addr == aend)				\
				break;					\
			addr += lsize;					\
		}							\
	} else {							\
		while (1) {						\
			protected_cache_op(hitop, addr);		\
			if (addr == aend)				\
				break;					\
			addr += lsize;					\
		}                                                       \
									\
	}								\
	__##pfx##flush_epilogue						\
}

__BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
__BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)

#endif
__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
	protected_, loongson2_)
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
/* blast_inv_dcache_range */
__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )

/* Currently, this is very specific to Loongson-3 */
#define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize)	\
static inline void blast_##pfx##cache##lsize##_node(long node)		\
{									\
	unsigned long start = CAC_BASE | nid_to_addrbase(node);		\
	unsigned long end = start + current_cpu_data.desc.waysize;	\
	unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;	\
	unsigned long ws_end = current_cpu_data.desc.ways <<		\
			       current_cpu_data.desc.waybit;		\
	unsigned long ws, addr;						\
									\
	for (ws = 0; ws < ws_end; ws += ws_inc)				\
		for (addr = start; addr < end; addr += lsize * 32)	\
			cache##lsize##_unroll32(addr|ws, indexop);	\
}

__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)

#endif /* _ASM_R4KCACHE_H */