OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:15 AM	rwxr-xr-x
📄 Kbuild	658 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	1.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	2.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin-global.h	2.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin-lq035q1.h	868 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin5xx_spi.h	2.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_can.h	36.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_dma.h	5.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_pfmon.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_ppi.h	9.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_sdh.h	7.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_serial.h	17.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_simple_timer.h	949 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_sport.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_sport3.h	5.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_twi.h	6.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_watchdog.h	696 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfrom.h	3.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	3.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 blackfin.h	1.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	1.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	3.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cdef_LPBlackfin.h	18.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	899 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 clkdev.h	318 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 clocks.h	1.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 context.S	5.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cplb.h	4.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cplbinit.h	1.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu.h	443 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 def_LPBlackfin.h	28.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	917 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	9.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dpmc.h	18.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 early_printk.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	4.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 entry.h	5.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exec.h	37 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixed_code.h	806 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 flat.h	1.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gpio.h	5.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gptimers.h	8.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	301 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	1.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ipipe.h	5.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ipipe_base.h	2.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	879 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_handler.h	1.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	7.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	3.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 l1layout.h	879 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	205 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mem_init.h	13.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mem_map.h	1.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	713 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	5.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	410 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 nand.h	895 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 nmi.h	195 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	546 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_offset.h	192 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	310 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pda.h	1.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	23 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm.h	590 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 portmux.h	16.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	3.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pseudo_instructions.h	391 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reboot.h	446 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rwlock.h	142 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 scb.h	445 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 segment.h	226 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	1.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	495 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	997 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	2.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 time.h	1.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	477 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	481 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	88 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 trace.h	2.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	4.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	5.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	523 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	29 bytes	01/28/2018 09:20:33 PM	rw-r--r--

Name

Size

Modified

Perms

📁 ..

11/17/2022 06:42:15 AM

rwxr-xr-x

📄 Kbuild

658 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 asm-offsets.h

35 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 atomic.h

1.55 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 barrier.h

2.55 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bfin-global.h

2.8 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bfin-lq035q1.h

868 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 bfin5xx_spi.h

2.07 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bfin_can.h

36.04 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bfin_dma.h

5.46 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bfin_pfmon.h

1.11 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bfin_ppi.h

9.01 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bfin_sdh.h

7.2 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bfin_serial.h

17.02 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bfin_simple_timer.h

949 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 bfin_sport.h

1.21 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bfin_sport3.h

5.47 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bfin_twi.h

6.25 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bfin_watchdog.h

696 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 bfrom.h

3.36 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bitops.h

3.45 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 blackfin.h

1.55 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bug.h

1.49 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cache.h

1.47 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cacheflush.h

3.79 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cdef_LPBlackfin.h

18.93 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 checksum.h

899 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 clkdev.h

318 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 clocks.h

1.66 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cmpxchg.h

3.2 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 context.S

5.92 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cplb.h

4.86 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cplbinit.h

1.6 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cpu.h

443 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 def_LPBlackfin.h

28.6 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 delay.h

917 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 dma-mapping.h

1.09 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 dma.h

9.28 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 dpmc.h

18.24 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 early_printk.h

1.09 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 elf.h

4.88 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 entry.h

5.27 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 exec.h

37 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 fixed_code.h

806 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 flat.h

1.41 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 ftrace.h

1.37 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 gpio.h

5.91 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 gptimers.h

8.95 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 hardirq.h

301 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 io.h

1.52 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 ipipe.h

5.81 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 ipipe_base.h

2.38 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 irq.h

879 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 irq_handler.h

1.93 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 irqflags.h

7.13 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 kgdb.h

3.23 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 l1layout.h

879 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 linkage.h

205 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 mem_init.h

13.1 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 mem_map.h

1.73 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu.h

713 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu_context.h

5.35 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 module.h

410 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 nand.h

895 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 nmi.h

195 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 page.h

546 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 page_offset.h

192 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 pci.h

310 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 pda.h

1.86 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 perf_event.h

23 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgtable.h

3 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pm.h

590 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 portmux.h

16.38 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 processor.h

3.21 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pseudo_instructions.h

391 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 ptrace.h

1.19 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 reboot.h

446 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 rwlock.h

142 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 scb.h

445 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 sections.h

2 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 segment.h

226 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 smp.h

1.34 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 spinlock.h

1.87 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 spinlock_types.h

495 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 string.h

1.04 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 switch_to.h

997 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 syscall.h

2.15 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 thread_info.h

2.66 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 time.h

1.33 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 timex.h

477 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 tlb.h

481 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 tlbflush.h

88 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 trace.h

2.67 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 traps.h

4.87 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 uaccess.h

5.79 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 unistd.h

523 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 vga.h

29 bytes

01/28/2018 09:20:33 PM

rw-r--r--

Editing: traps.h

/*
 *  Copyright 2004-2009 Analog Devices Inc.
 *                 2001 Lineo, Inc
 *                        Tony Kou
 *                 1993 Hamish Macdonald
 *
 * Licensed under the GPL-2
 */

#ifndef _BFIN_TRAPS_H
#define _BFIN_TRAPS_H

#define VEC_SYS		(0)
#define VEC_EXCPT01	(1)
#define VEC_EXCPT02	(2)
#define VEC_EXCPT03	(3)
#define VEC_EXCPT04	(4)
#define VEC_EXCPT05	(5)
#define VEC_EXCPT06	(6)
#define VEC_EXCPT07	(7)
#define VEC_EXCPT08	(8)
#define VEC_EXCPT09	(9)
#define VEC_EXCPT10	(10)
#define VEC_EXCPT11	(11)
#define VEC_EXCPT12	(12)
#define VEC_EXCPT13	(13)
#define VEC_EXCPT14	(14)
#define VEC_EXCPT15	(15)
#define VEC_STEP	(16)
#define VEC_OVFLOW	(17)
#define VEC_UNDEF_I	(33)
#define VEC_ILGAL_I	(34)
#define VEC_CPLB_VL	(35)
#define VEC_MISALI_D	(36)
#define VEC_UNCOV	(37)
#define VEC_CPLB_M	(38)
#define VEC_CPLB_MHIT	(39)
#define VEC_WATCH	(40)
#define VEC_ISTRU_VL	(41)	/*ADSP-BF535 only (MH) */
#define VEC_MISALI_I	(42)
#define VEC_CPLB_I_VL	(43)
#define VEC_CPLB_I_M	(44)
#define VEC_CPLB_I_MHIT	(45)
#define VEC_ILL_RES	(46)	/* including unvalid supervisor mode insn */
/* The hardware reserves (63) for future use - we use it to tell our
 * normal exception handling code we have a hardware error
 */
#define VEC_HWERR	(63)

#ifndef __ASSEMBLY__

#define HWC_x2(level) \
	"System MMR Error\n" \
	level " - An error occurred due to an invalid access to an System MMR location\n" \
	level "   Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
	level "   or a 16-bit register is accessed with a 32-bit instruction.\n"
#define HWC_x3(level) \
	"External Memory Addressing Error\n"
#define EXC_0x04(level) \
	"Unimplmented exception occurred\n" \
	level " - Maybe you forgot to install a custom exception handler?\n"
#define HWC_x12(level) \
	"Performance Monitor Overflow\n"
#define HWC_x18(level) \
	"RAISE 5 instruction\n" \
	level "    Software issued a RAISE 5 instruction to invoke the Hardware\n"
#define HWC_default(level) \
	 "Reserved\n"
#define EXC_0x03(level) \
	"Application stack overflow\n" \
	level " - Please increase the stack size of the application using elf2flt -s option,\n" \
	level "   and/or reduce the stack use of the application.\n"
#define EXC_0x10(level) \
	"Single step\n" \
	level " - When the processor is in single step mode, every instruction\n" \
	level "   generates an exception. Primarily used for debugging.\n"
#define EXC_0x11(level) \
	"Exception caused by a trace buffer full condition\n" \
	level " - The processor takes this exception when the trace\n" \
	level "   buffer overflows (only when enabled by the Trace Unit Control register).\n"
#define EXC_0x21(level) \
	"Undefined instruction\n" \
	level " - May be used to emulate instructions that are not defined for\n" \
	level "   a particular processor implementation.\n"
#define EXC_0x22(level) \
	"Illegal instruction combination\n" \
	level " - See section for multi-issue rules in the Blackfin\n" \
	level "   Processor Instruction Set Reference.\n"
#define EXC_0x23(level) \
	"Data access CPLB protection violation\n" \
	level " - Attempted read or write to Supervisor resource,\n" \
	level "   or illegal data memory access. \n"
#define EXC_0x24(level) \
	"Data access misaligned address violation\n" \
	level " - Attempted misaligned data memory or data cache access.\n"
#define EXC_0x25(level) \
	"Unrecoverable event\n" \
	level " - For example, an exception generated while processing a previous exception.\n"
#define EXC_0x26(level) \
	"Data access CPLB miss\n" \
	level " - Used by the MMU to signal a CPLB miss on a data access.\n"
#define EXC_0x27(level) \
	"Data access multiple CPLB hits\n" \
	level " - More than one CPLB entry matches data fetch address.\n"
#define EXC_0x28(level) \
	"Program Sequencer Exception caused by an emulation watchpoint match\n" \
	level " - There is a watchpoint match, and one of the EMUSW\n" \
	level "   bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
#define EXC_0x2A(level) \
	"Instruction fetch misaligned address violation\n" \
	level " - Attempted misaligned instruction cache fetch.\n"
#define EXC_0x2B(level) \
	"CPLB protection violation\n" \
	level " - Illegal instruction fetch access (memory protection violation).\n"
#define EXC_0x2C(level) \
	"Instruction fetch CPLB miss\n" \
	level " - CPLB miss on an instruction fetch.\n"
#define EXC_0x2D(level) \
	"Instruction fetch multiple CPLB hits\n" \
	level " - More than one CPLB entry matches instruction fetch address.\n"
#define EXC_0x2E(level) \
	"Illegal use of supervisor resource\n" \
	level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
	level "   Supervisor resources are registers and instructions that are reserved\n" \
	level "   for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
	level "   only instructions.\n"

extern void double_fault_c(struct pt_regs *fp);

#endif				/* __ASSEMBLY__ */
#endif				/* _BFIN_TRAPS_H */