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11/17/2022 06:42:15 AM
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Kbuild
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asm-offsets.h
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atomic.h
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barrier.h
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bfin-global.h
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bfin-lq035q1.h
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bfin5xx_spi.h
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bitops.h
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blackfin.h
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bug.h
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cache.h
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cacheflush.h
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cdef_LPBlackfin.h
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checksum.h
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clkdev.h
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clocks.h
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cmpxchg.h
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context.S
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cplb.h
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cplbinit.h
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cpu.h
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def_LPBlackfin.h
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delay.h
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dma-mapping.h
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dma.h
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early_printk.h
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elf.h
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entry.h
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gpio.h
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gptimers.h
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hardirq.h
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irq.h
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irq_handler.h
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kgdb.h
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l1layout.h
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mem_init.h
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mem_map.h
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mmu_context.h
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module.h
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page_offset.h
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pci.h
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pda.h
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perf_event.h
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pgtable.h
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pm.h
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portmux.h
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processor.h
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pseudo_instructions.h
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ptrace.h
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reboot.h
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rwlock.h
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scb.h
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sections.h
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segment.h
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smp.h
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spinlock.h
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spinlock_types.h
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string.h
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switch_to.h
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syscall.h
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thread_info.h
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time.h
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timex.h
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tlb.h
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tlbflush.h
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trace.h
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traps.h
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uaccess.h
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unistd.h
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vga.h
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Editing: barrier.h
Close
/* * Copyright 2004-2009 Analog Devices Inc. * Tony Kou (tonyko@lineo.ca) * * Licensed under the GPL-2 or later */ #ifndef _BLACKFIN_BARRIER_H #define _BLACKFIN_BARRIER_H #include <asm/cache.h> #define nop() __asm__ __volatile__ ("nop;\n\t" : : ) /* * Force strict CPU ordering. */ #ifdef CONFIG_SMP #ifdef __ARCH_SYNC_CORE_DCACHE /* Force Core data cache coherence */ # define mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0) # define rmb() do { barrier(); smp_check_barrier(); } while (0) # define wmb() do { barrier(); smp_mark_barrier(); } while (0) /* * read_barrier_depends - Flush all pending reads that subsequents reads * depend on. * * No data-dependent reads from memory-like regions are ever reordered * over this barrier. All reads preceding this primitive are guaranteed * to access memory (but not necessarily other CPUs' caches) before any * reads following this primitive that depend on the data return by * any of the preceding reads. This primitive is much lighter weight than * rmb() on most CPUs, and is never heavier weight than is * rmb(). * * These ordering constraints are respected by both the local CPU * and the compiler. * * Ordering is not guaranteed by anything other than these primitives, * not even by data dependencies. See the documentation for * memory_barrier() for examples and URLs to more information. * * For example, the following code would force ordering (the initial * value of "a" is zero, "b" is one, and "p" is "&a"): * * <programlisting> * CPU 0 CPU 1 * * b = 2; * memory_barrier(); * p = &b; q = p; * read_barrier_depends(); * d = *q; * </programlisting> * * because the read of "*q" depends on the read of "p" and these * two reads are separated by a read_barrier_depends(). However, * the following code, with the same initial values for "a" and "b": * * <programlisting> * CPU 0 CPU 1 * * a = 2; * memory_barrier(); * b = 3; y = b; * read_barrier_depends(); * x = a; * </programlisting> * * does not enforce ordering, since there is no data dependency between * the read of "a" and the read of "b". Therefore, on some CPUs, such * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() * in cases like this where there are no data dependencies. */ # define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0) #endif #endif /* !CONFIG_SMP */ #define __smp_mb__before_atomic() barrier() #define __smp_mb__after_atomic() barrier() #include <asm-generic/barrier.h> #endif /* _BLACKFIN_BARRIER_H */