OXIESEC PANEL
- Current Dir:
/
/
usr
/
src
/
linux-headers-4.15.0-197
/
arch
/
blackfin
/
include
/
asm
Server IP: 139.59.38.164
Upload:
Create Dir:
Name
Size
Modified
Perms
📁
..
-
11/17/2022 06:42:15 AM
rwxr-xr-x
📄
Kbuild
658 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
asm-offsets.h
35 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
atomic.h
1.55 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
barrier.h
2.55 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin-global.h
2.8 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin-lq035q1.h
868 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin5xx_spi.h
2.07 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_can.h
36.04 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_dma.h
5.46 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_pfmon.h
1.11 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_ppi.h
9.01 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_sdh.h
7.2 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_serial.h
17.02 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_simple_timer.h
949 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_sport.h
1.21 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_sport3.h
5.47 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_twi.h
6.25 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_watchdog.h
696 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfrom.h
3.36 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bitops.h
3.45 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
blackfin.h
1.55 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bug.h
1.49 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cache.h
1.47 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cacheflush.h
3.79 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cdef_LPBlackfin.h
18.93 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
checksum.h
899 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
clkdev.h
318 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
clocks.h
1.66 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cmpxchg.h
3.2 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
context.S
5.92 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cplb.h
4.86 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cplbinit.h
1.6 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cpu.h
443 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
def_LPBlackfin.h
28.6 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
delay.h
917 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
dma-mapping.h
1.09 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
dma.h
9.28 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
dpmc.h
18.24 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
early_printk.h
1.09 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
elf.h
4.88 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
entry.h
5.27 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
exec.h
37 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
fixed_code.h
806 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
flat.h
1.41 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ftrace.h
1.37 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
gpio.h
5.91 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
gptimers.h
8.95 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
hardirq.h
301 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
io.h
1.52 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ipipe.h
5.81 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ipipe_base.h
2.38 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
irq.h
879 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
irq_handler.h
1.93 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
irqflags.h
7.13 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
kgdb.h
3.23 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
l1layout.h
879 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
linkage.h
205 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
mem_init.h
13.1 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mem_map.h
1.73 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mmu.h
713 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
mmu_context.h
5.35 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
module.h
410 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
nand.h
895 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
nmi.h
195 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
page.h
546 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
page_offset.h
192 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
pci.h
310 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
pda.h
1.86 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
perf_event.h
23 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
pgtable.h
3 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
pm.h
590 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
portmux.h
16.38 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
processor.h
3.21 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
pseudo_instructions.h
391 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
ptrace.h
1.19 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
reboot.h
446 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
rwlock.h
142 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
scb.h
445 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
sections.h
2 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
segment.h
226 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
smp.h
1.34 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
spinlock.h
1.87 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
spinlock_types.h
495 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
string.h
1.04 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
switch_to.h
997 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
syscall.h
2.15 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
thread_info.h
2.66 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
time.h
1.33 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
timex.h
477 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
tlb.h
481 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
tlbflush.h
88 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
trace.h
2.67 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
traps.h
4.87 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
uaccess.h
5.79 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
unistd.h
523 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
vga.h
29 bytes
01/28/2018 09:20:33 PM
rw-r--r--
Editing: ipipe.h
Close
/* -*- linux-c -*- * include/asm-blackfin/ipipe.h * * Copyright (C) 2002-2007 Philippe Gerum. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139, * USA; either version 2 of the License, or (at your option) any later * version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __ASM_BLACKFIN_IPIPE_H #define __ASM_BLACKFIN_IPIPE_H #ifdef CONFIG_IPIPE #include <linux/cpumask.h> #include <linux/list.h> #include <linux/threads.h> #include <linux/irq.h> #include <linux/ipipe_percpu.h> #include <asm/ptrace.h> #include <asm/irq.h> #include <asm/bitops.h> #include <linux/atomic.h> #include <asm/traps.h> #include <asm/bitsperlong.h> #define IPIPE_ARCH_STRING "1.16-01" #define IPIPE_MAJOR_NUMBER 1 #define IPIPE_MINOR_NUMBER 16 #define IPIPE_PATCH_NUMBER 1 #ifdef CONFIG_SMP #error "I-pipe/blackfin: SMP not implemented" #else /* !CONFIG_SMP */ #define ipipe_processor_id() 0 #endif /* CONFIG_SMP */ #define prepare_arch_switch(next) \ do { \ ipipe_schedule_notify(current, next); \ hard_local_irq_disable(); \ } while (0) #define task_hijacked(p) \ ({ \ int __x__ = __ipipe_root_domain_p; \ if (__x__) \ hard_local_irq_enable(); \ !__x__; \ }) struct ipipe_domain; struct ipipe_sysinfo { int sys_nr_cpus; /* Number of CPUs on board */ int sys_hrtimer_irq; /* hrtimer device IRQ */ u64 sys_hrtimer_freq; /* hrtimer device frequency */ u64 sys_hrclock_freq; /* hrclock device frequency */ u64 sys_cpu_freq; /* CPU frequency (Hz) */ }; #define ipipe_read_tsc(t) \ ({ \ unsigned long __cy2; \ __asm__ __volatile__ ("1: %0 = CYCLES2\n" \ "%1 = CYCLES\n" \ "%2 = CYCLES2\n" \ "CC = %2 == %0\n" \ "if ! CC jump 1b\n" \ : "=d,a" (((unsigned long *)&t)[1]), \ "=d,a" (((unsigned long *)&t)[0]), \ "=d,a" (__cy2) \ : /*no input*/ : "CC"); \ t; \ }) #define ipipe_cpu_freq() __ipipe_core_clock #define ipipe_tsc2ns(_t) (((unsigned long)(_t)) * __ipipe_freq_scale) #define ipipe_tsc2us(_t) (ipipe_tsc2ns(_t) / 1000 + 1) /* Private interface -- Internal use only */ #define __ipipe_check_platform() do { } while (0) #define __ipipe_init_platform() do { } while (0) extern atomic_t __ipipe_irq_lvdepth[IVG15 + 1]; extern unsigned long __ipipe_irq_lvmask; extern struct ipipe_domain ipipe_root; /* enable/disable_irqdesc _must_ be used in pairs. */ void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq); void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq); #define __ipipe_enable_irq(irq) \ do { \ struct irq_desc *desc = irq_to_desc(irq); \ struct irq_chip *chip = get_irq_desc_chip(desc); \ chip->irq_unmask(&desc->irq_data); \ } while (0) #define __ipipe_disable_irq(irq) \ do { \ struct irq_desc *desc = irq_to_desc(irq); \ struct irq_chip *chip = get_irq_desc_chip(desc); \ chip->irq_mask(&desc->irq_data); \ } while (0) static inline int __ipipe_check_tickdev(const char *devname) { return 1; } void __ipipe_enable_pipeline(void); #define __ipipe_hook_critical_ipi(ipd) do { } while (0) void ___ipipe_sync_pipeline(void); void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs); int __ipipe_get_irq_priority(unsigned int irq); void __ipipe_serial_debug(const char *fmt, ...); asmlinkage void __ipipe_call_irqtail(unsigned long addr); DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs); extern unsigned long __ipipe_core_clock; extern unsigned long __ipipe_freq_scale; extern unsigned long __ipipe_irq_tail_hook; static inline unsigned long __ipipe_ffnz(unsigned long ul) { return ffs(ul) - 1; } #define __ipipe_do_root_xirq(ipd, irq) \ ((ipd)->irqs[irq].handler(irq, raw_cpu_ptr(&__ipipe_tick_regs))) #define __ipipe_run_irqtail(irq) /* Must be a macro */ \ do { \ unsigned long __pending; \ CSYNC(); \ __pending = bfin_read_IPEND(); \ if (__pending & 0x8000) { \ __pending &= ~0x8010; \ if (__pending && (__pending & (__pending - 1)) == 0) \ __ipipe_call_irqtail(__ipipe_irq_tail_hook); \ } \ } while (0) #define __ipipe_syscall_watched_p(p, sc) \ (ipipe_notifier_enabled_p(p) || (unsigned long)sc >= NR_syscalls) #ifdef CONFIG_BF561 #define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val) #define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val) #define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val) #define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS() #elif defined(CONFIG_BF54x) #define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val) #define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val) #define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val) #define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val) #endif #define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0) #else /* !CONFIG_IPIPE */ #define task_hijacked(p) 0 #define ipipe_trap_notify(t, r) 0 #define __ipipe_root_tick_p(regs) 1 #endif /* !CONFIG_IPIPE */ #ifdef CONFIG_TICKSOURCE_CORETMR #define IRQ_SYSTMR IRQ_CORETMR #define IRQ_PRIOTMR IRQ_CORETMR #else #define IRQ_SYSTMR IRQ_TIMER0 #define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 #endif #define ipipe_update_tick_evtdev(evtdev) do { } while (0) #endif /* !__ASM_BLACKFIN_IPIPE_H */