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11/17/2022 06:42:15 AM
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Kbuild
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a.out-core.h
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asm-offsets.h
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atomic.h
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device.h
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hw_irq.h
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irq.h
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irq_regs.h
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irqflags.h
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pci.h
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percpu.h
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perf_event.h
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pgalloc.h
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signal.h
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smp.h
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socket.h
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special_insns.h
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spinlock.h
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spinlock_types.h
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string.h
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switch_to.h
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syscall.h
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termios.h
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thread_info.h
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timex.h
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tlb.h
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tlbflush.h
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topology.h
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types.h
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uaccess.h
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ucontext.h
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unaligned.h
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unistd.h
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user.h
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vga.h
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word-at-a-time.h
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wrperfmon.h
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xchg.h
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xor.h
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Editing: xchg.h
Close
/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_CMPXCHG_H #error Do not include xchg.h directly! #else /* * xchg/xchg_local and cmpxchg/cmpxchg_local share the same code * except that local version do not have the expensive memory barrier. * So this file is included twice from asm/cmpxchg.h. */ /* * Atomic exchange. * Since it can be used to implement critical sections * it must clobber "memory" (also for interrupts in UP). * * The leading and the trailing memory barriers guarantee that these * operations are fully ordered. * */ static inline unsigned long ____xchg(_u8, volatile char *m, unsigned long val) { unsigned long ret, tmp, addr64; smp_mb(); __asm__ __volatile__( " andnot %4,7,%3\n" " insbl %1,%4,%1\n" "1: ldq_l %2,0(%3)\n" " extbl %2,%4,%0\n" " mskbl %2,%4,%2\n" " or %1,%2,%2\n" " stq_c %2,0(%3)\n" " beq %2,2f\n" __ASM__MB ".subsection 2\n" "2: br 1b\n" ".previous" : "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64) : "r" ((long)m), "1" (val) : "memory"); return ret; } static inline unsigned long ____xchg(_u16, volatile short *m, unsigned long val) { unsigned long ret, tmp, addr64; smp_mb(); __asm__ __volatile__( " andnot %4,7,%3\n" " inswl %1,%4,%1\n" "1: ldq_l %2,0(%3)\n" " extwl %2,%4,%0\n" " mskwl %2,%4,%2\n" " or %1,%2,%2\n" " stq_c %2,0(%3)\n" " beq %2,2f\n" __ASM__MB ".subsection 2\n" "2: br 1b\n" ".previous" : "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64) : "r" ((long)m), "1" (val) : "memory"); return ret; } static inline unsigned long ____xchg(_u32, volatile int *m, unsigned long val) { unsigned long dummy; smp_mb(); __asm__ __volatile__( "1: ldl_l %0,%4\n" " bis $31,%3,%1\n" " stl_c %1,%2\n" " beq %1,2f\n" __ASM__MB ".subsection 2\n" "2: br 1b\n" ".previous" : "=&r" (val), "=&r" (dummy), "=m" (*m) : "rI" (val), "m" (*m) : "memory"); return val; } static inline unsigned long ____xchg(_u64, volatile long *m, unsigned long val) { unsigned long dummy; smp_mb(); __asm__ __volatile__( "1: ldq_l %0,%4\n" " bis $31,%3,%1\n" " stq_c %1,%2\n" " beq %1,2f\n" __ASM__MB ".subsection 2\n" "2: br 1b\n" ".previous" : "=&r" (val), "=&r" (dummy), "=m" (*m) : "rI" (val), "m" (*m) : "memory"); return val; } /* This function doesn't exist, so you'll get a linker error if something tries to do an invalid xchg(). */ extern void __xchg_called_with_bad_pointer(void); static __always_inline unsigned long ____xchg(, volatile void *ptr, unsigned long x, int size) { switch (size) { case 1: return ____xchg(_u8, ptr, x); case 2: return ____xchg(_u16, ptr, x); case 4: return ____xchg(_u32, ptr, x); case 8: return ____xchg(_u64, ptr, x); } __xchg_called_with_bad_pointer(); return x; } /* * Atomic compare and exchange. Compare OLD with MEM, if identical, * store NEW in MEM. Return the initial value in MEM. Success is * indicated by comparing RETURN with OLD. * * The leading and the trailing memory barriers guarantee that these * operations are fully ordered. * * The trailing memory barrier is placed in SMP unconditionally, in * order to guarantee that dependency ordering is preserved when a * dependency is headed by an unsuccessful operation. */ static inline unsigned long ____cmpxchg(_u8, volatile char *m, unsigned char old, unsigned char new) { unsigned long prev, tmp, cmp, addr64; smp_mb(); __asm__ __volatile__( " andnot %5,7,%4\n" " insbl %1,%5,%1\n" "1: ldq_l %2,0(%4)\n" " extbl %2,%5,%0\n" " cmpeq %0,%6,%3\n" " beq %3,2f\n" " mskbl %2,%5,%2\n" " or %1,%2,%2\n" " stq_c %2,0(%4)\n" " beq %2,3f\n" "2:\n" __ASM__MB ".subsection 2\n" "3: br 1b\n" ".previous" : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64) : "r" ((long)m), "Ir" (old), "1" (new) : "memory"); return prev; } static inline unsigned long ____cmpxchg(_u16, volatile short *m, unsigned short old, unsigned short new) { unsigned long prev, tmp, cmp, addr64; smp_mb(); __asm__ __volatile__( " andnot %5,7,%4\n" " inswl %1,%5,%1\n" "1: ldq_l %2,0(%4)\n" " extwl %2,%5,%0\n" " cmpeq %0,%6,%3\n" " beq %3,2f\n" " mskwl %2,%5,%2\n" " or %1,%2,%2\n" " stq_c %2,0(%4)\n" " beq %2,3f\n" "2:\n" __ASM__MB ".subsection 2\n" "3: br 1b\n" ".previous" : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64) : "r" ((long)m), "Ir" (old), "1" (new) : "memory"); return prev; } static inline unsigned long ____cmpxchg(_u32, volatile int *m, int old, int new) { unsigned long prev, cmp; smp_mb(); __asm__ __volatile__( "1: ldl_l %0,%5\n" " cmpeq %0,%3,%1\n" " beq %1,2f\n" " mov %4,%1\n" " stl_c %1,%2\n" " beq %1,3f\n" "2:\n" __ASM__MB ".subsection 2\n" "3: br 1b\n" ".previous" : "=&r"(prev), "=&r"(cmp), "=m"(*m) : "r"((long) old), "r"(new), "m"(*m) : "memory"); return prev; } static inline unsigned long ____cmpxchg(_u64, volatile long *m, unsigned long old, unsigned long new) { unsigned long prev, cmp; smp_mb(); __asm__ __volatile__( "1: ldq_l %0,%5\n" " cmpeq %0,%3,%1\n" " beq %1,2f\n" " mov %4,%1\n" " stq_c %1,%2\n" " beq %1,3f\n" "2:\n" __ASM__MB ".subsection 2\n" "3: br 1b\n" ".previous" : "=&r"(prev), "=&r"(cmp), "=m"(*m) : "r"((long) old), "r"(new), "m"(*m) : "memory"); return prev; } /* This function doesn't exist, so you'll get a linker error if something tries to do an invalid cmpxchg(). */ extern void __cmpxchg_called_with_bad_pointer(void); static __always_inline unsigned long ____cmpxchg(, volatile void *ptr, unsigned long old, unsigned long new, int size) { switch (size) { case 1: return ____cmpxchg(_u8, ptr, old, new); case 2: return ____cmpxchg(_u16, ptr, old, new); case 4: return ____cmpxchg(_u32, ptr, old, new); case 8: return ____cmpxchg(_u64, ptr, old, new); } __cmpxchg_called_with_bad_pointer(); return old; } #endif