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11/17/2022 06:42:15 AM
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Kbuild
320 bytes
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a.out-core.h
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a.out.h
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agp.h
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agp_backend.h
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asm-offsets.h
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asm-prototypes.h
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atomic.h
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barrier.h
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bitops.h
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bug.h
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bugs.h
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cache.h
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cacheflush.h
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checksum.h
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cmpxchg.h
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compiler.h
498 bytes
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console.h
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core_apecs.h
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core_cia.h
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core_irongate.h
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core_lca.h
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core_marvel.h
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core_mcpcia.h
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core_polaris.h
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core_t2.h
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core_titan.h
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core_tsunami.h
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core_wildfire.h
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delay.h
264 bytes
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device.h
129 bytes
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div64.h
31 bytes
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dma-mapping.h
276 bytes
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dma.h
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elf.h
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emergency-restart.h
149 bytes
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err_common.h
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err_ev6.h
116 bytes
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err_ev7.h
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extable.h
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floppy.h
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fpu.h
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ftrace.h
12 bytes
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futex.h
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gct.h
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hardirq.h
223 bytes
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hw_irq.h
302 bytes
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hwrpb.h
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io.h
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io_trivial.h
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irq.h
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irq_regs.h
34 bytes
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irqflags.h
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jensen.h
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kdebug.h
32 bytes
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kmap_types.h
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linkage.h
256 bytes
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local.h
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local64.h
33 bytes
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machvec.h
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mc146818rtc.h
680 bytes
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mce.h
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mmu.h
203 bytes
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mmu_context.h
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mmzone.h
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module.h
329 bytes
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page.h
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pal.h
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param.h
284 bytes
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parport.h
536 bytes
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pci.h
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percpu.h
527 bytes
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perf_event.h
105 bytes
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pgalloc.h
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pgtable.h
13.17 KB
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processor.h
2.07 KB
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ptrace.h
754 bytes
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rwsem.h
4.62 KB
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segment.h
132 bytes
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serial.h
1.01 KB
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sfp-machine.h
2.86 KB
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shmparam.h
191 bytes
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signal.h
627 bytes
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smp.h
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socket.h
310 bytes
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special_insns.h
925 bytes
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spinlock.h
2.85 KB
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spinlock_types.h
413 bytes
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string.h
2.42 KB
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switch_to.h
406 bytes
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syscall.h
235 bytes
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termios.h
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thread_info.h
3.63 KB
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timex.h
827 bytes
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tlb.h
473 bytes
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tlbflush.h
3.37 KB
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topology.h
957 bytes
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types.h
143 bytes
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uaccess.h
9.56 KB
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ucontext.h
348 bytes
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unaligned.h
340 bytes
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unistd.h
494 bytes
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user.h
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vga.h
2 KB
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word-at-a-time.h
1.34 KB
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wrperfmon.h
2.56 KB
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xchg.h
5.74 KB
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xor.h
21.71 KB
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Editing: wrperfmon.h
Close
/* SPDX-License-Identifier: GPL-2.0 */ /* * Definitions for use with the Alpha wrperfmon PAL call. */ #ifndef __ALPHA_WRPERFMON_H #define __ALPHA_WRPERFMON_H /* Following commands are implemented on all CPUs */ #define PERFMON_CMD_DISABLE 0 #define PERFMON_CMD_ENABLE 1 #define PERFMON_CMD_DESIRED_EVENTS 2 #define PERFMON_CMD_LOGGING_OPTIONS 3 /* Following commands on EV5/EV56/PCA56 only */ #define PERFMON_CMD_INT_FREQ 4 #define PERFMON_CMD_ENABLE_CLEAR 7 /* Following commands are on EV5 and better CPUs */ #define PERFMON_CMD_READ 5 #define PERFMON_CMD_WRITE 6 /* Following command are on EV6 and better CPUs */ #define PERFMON_CMD_ENABLE_WRITE 7 /* Following command are on EV67 and better CPUs */ #define PERFMON_CMD_I_STAT 8 #define PERFMON_CMD_PMPC 9 /* EV5/EV56/PCA56 Counters */ #define EV5_PCTR_0 (1UL<<0) #define EV5_PCTR_1 (1UL<<1) #define EV5_PCTR_2 (1UL<<2) #define EV5_PCTR_0_COUNT_SHIFT 48 #define EV5_PCTR_1_COUNT_SHIFT 32 #define EV5_PCTR_2_COUNT_SHIFT 16 #define EV5_PCTR_0_COUNT_MASK 0xffffUL #define EV5_PCTR_1_COUNT_MASK 0xffffUL #define EV5_PCTR_2_COUNT_MASK 0x3fffUL /* EV6 Counters */ #define EV6_PCTR_0 (1UL<<0) #define EV6_PCTR_1 (1UL<<1) #define EV6_PCTR_0_COUNT_SHIFT 28 #define EV6_PCTR_1_COUNT_SHIFT 6 #define EV6_PCTR_0_COUNT_MASK 0xfffffUL #define EV6_PCTR_1_COUNT_MASK 0xfffffUL /* EV67 (and subsequent) counters */ #define EV67_PCTR_0 (1UL<<0) #define EV67_PCTR_1 (1UL<<1) #define EV67_PCTR_0_COUNT_SHIFT 28 #define EV67_PCTR_1_COUNT_SHIFT 6 #define EV67_PCTR_0_COUNT_MASK 0xfffffUL #define EV67_PCTR_1_COUNT_MASK 0xfffffUL /* * The Alpha Architecure Handbook, vers. 4 (1998) appears to have a misprint * in Table E-23 regarding the bits that set the event PCTR 1 counts. * Hopefully what we have here is correct. */ #define EV6_PCTR_0_EVENT_MASK 0x10UL #define EV6_PCTR_1_EVENT_MASK 0x0fUL /* EV6 Events */ #define EV6_PCTR_0_CYCLES (0UL << 4) #define EV6_PCTR_0_INSTRUCTIONS (1UL << 4) #define EV6_PCTR_1_CYCLES 0 #define EV6_PCTR_1_BRANCHES 1 #define EV6_PCTR_1_BRANCH_MISPREDICTS 2 #define EV6_PCTR_1_DTB_SINGLE_MISSES 3 #define EV6_PCTR_1_DTB_DOUBLE_MISSES 4 #define EV6_PCTR_1_ITB_MISSES 5 #define EV6_PCTR_1_UNALIGNED_TRAPS 6 #define EV6_PCTR_1_REPLY_TRAPS 7 /* From the Alpha Architecture Reference Manual, 4th edn., 2002 */ #define EV67_PCTR_MODE_MASK 0x10UL #define EV67_PCTR_EVENT_MASK 0x0CUL #define EV67_PCTR_MODE_PROFILEME (1UL<<4) #define EV67_PCTR_MODE_AGGREGATE (0UL<<4) #define EV67_PCTR_INSTR_CYCLES (0UL<<2) #define EV67_PCTR_CYCLES_UNDEF (1UL<<2) #define EV67_PCTR_INSTR_BCACHEMISS (2UL<<2) #define EV67_PCTR_CYCLES_MBOX (3UL<<2) #endif