OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:12 AM	rwxr-xr-x
📄 Kbuild	290 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	4.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic_defs.h	4.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ax88796.h	751 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	720 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	7.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	445 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 busctl-regs.h	2.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	727 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	3.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	4.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	4.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu-irqs.h	2.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	685 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	1.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 div64.h	31 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dm9000.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	448 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	3.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	5.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 emergency-restart.h	149 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu.h	261 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	12 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	416 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 gdb-stub.h	4.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gpio-regs.h	3.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	666 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	4.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	484 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	9.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irc-regs.h	1.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	760 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_regs.h	764 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	3.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug.h	32 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	123 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	114 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 local.h	140 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 local64.h	33 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 math-emu.h	6.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mb-regs.h	6.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mb86943a.h	1.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mb93091-fpga-irqs.h	1.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mb93093-fpga-irqs.h	789 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mb93493-irqs.h	1.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mb93493-regs.h	12.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mem-layout.h	2.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	1.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	1.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	617 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	1.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu.h	147 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	487 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	1.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	16.02 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 processor.h	2.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	1.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 segment.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial-regs.h	1.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	308 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	641 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	183 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	141 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	139 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	516 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spr-regs.h	17.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	1.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	2.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 termios.h	425 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	3.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timer-regs.h	3.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	720 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	615 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	1.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	229 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 types.h	595 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	6.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ucontext.h	281 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	694 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	928 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	3.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	464 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 virtconvert.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 xor.h	29 bytes	01/28/2018 09:20:33 PM	rw-r--r--

Editing: bitops.h

/* bitops.h: bit operations for the Fujitsu FR-V CPUs
 *
 * For an explanation of how atomic ops work in this arch, see:
 *   Documentation/frv/atomic-ops.txt
 *
 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
 * Written by David Howells (dhowells@redhat.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#ifndef _ASM_BITOPS_H
#define _ASM_BITOPS_H

#include <linux/compiler.h>
#include <asm/byteorder.h>

#ifdef __KERNEL__

#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif

#include <asm-generic/bitops/ffz.h>

#include <asm/atomic.h>

static inline int test_and_clear_bit(unsigned long nr, volatile void *addr)
{
	unsigned int *ptr = (void *)addr;
	unsigned int mask = 1UL << (nr & 31);
	ptr += nr >> 5;
	return (__atomic32_fetch_and(~mask, ptr) & mask) != 0;
}

static inline int test_and_set_bit(unsigned long nr, volatile void *addr)
{
	unsigned int *ptr = (void *)addr;
	unsigned int mask = 1UL << (nr & 31);
	ptr += nr >> 5;
	return (__atomic32_fetch_or(mask, ptr) & mask) != 0;
}

static inline int test_and_change_bit(unsigned long nr, volatile void *addr)
{
	unsigned int *ptr = (void *)addr;
	unsigned int mask = 1UL << (nr & 31);
	ptr += nr >> 5;
	return (__atomic32_fetch_xor(mask, ptr) & mask) != 0;
}

static inline void clear_bit(unsigned long nr, volatile void *addr)
{
	test_and_clear_bit(nr, addr);
}

static inline void set_bit(unsigned long nr, volatile void *addr)
{
	test_and_set_bit(nr, addr);
}

static inline void change_bit(unsigned long nr, volatile void *addr)
{
	test_and_change_bit(nr, addr);
}

static inline void __clear_bit(unsigned long nr, volatile void *addr)
{
	volatile unsigned long *a = addr;
	int mask;

a += nr >> 5;
	mask = 1 << (nr & 31);
	*a &= ~mask;
}

static inline void __set_bit(unsigned long nr, volatile void *addr)
{
	volatile unsigned long *a = addr;
	int mask;

a += nr >> 5;
	mask = 1 << (nr & 31);
	*a |= mask;
}

static inline void __change_bit(unsigned long nr, volatile void *addr)
{
	volatile unsigned long *a = addr;
	int mask;

a += nr >> 5;
	mask = 1 << (nr & 31);
	*a ^= mask;
}

static inline int __test_and_clear_bit(unsigned long nr, volatile void *addr)
{
	volatile unsigned long *a = addr;
	int mask, retval;

a += nr >> 5;
	mask = 1 << (nr & 31);
	retval = (mask & *a) != 0;
	*a &= ~mask;
	return retval;
}

static inline int __test_and_set_bit(unsigned long nr, volatile void *addr)
{
	volatile unsigned long *a = addr;
	int mask, retval;

a += nr >> 5;
	mask = 1 << (nr & 31);
	retval = (mask & *a) != 0;
	*a |= mask;
	return retval;
}

static inline int __test_and_change_bit(unsigned long nr, volatile void *addr)
{
	volatile unsigned long *a = addr;
	int mask, retval;

a += nr >> 5;
	mask = 1 << (nr & 31);
	retval = (mask & *a) != 0;
	*a ^= mask;
	return retval;
}

/*
 * This routine doesn't need to be atomic.
 */
static inline int
__constant_test_bit(unsigned long nr, const volatile void *addr)
{
	return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
}

static inline int __test_bit(unsigned long nr, const volatile void *addr)
{
	int 	* a = (int *) addr;
	int	mask;

a += nr >> 5;
	mask = 1 << (nr & 0x1f);
	return ((mask & *a) != 0);
}

#define test_bit(nr,addr) \
(__builtin_constant_p(nr) ? \
 __constant_test_bit((nr),(addr)) : \
 __test_bit((nr),(addr)))

#include <asm-generic/bitops/find.h>

/**
 * fls - find last bit set
 * @x: the word to search
 *
 * This is defined the same way as ffs:
 * - return 32..1 to indicate bit 31..0 most significant bit set
 * - return 0 to indicate no bits set
 */
#define fls(x)						\
({							\
	int bit;					\
							\
	asm("	subcc	%1,gr0,gr0,icc0		\n"	\
	    "	ckne	icc0,cc4		\n"	\
	    "	cscan.p	%1,gr0,%0	,cc4,#1	\n"	\
	    "	csub	%0,%0,%0	,cc4,#0	\n"	\
	    "   csub    %2,%0,%0	,cc4,#1	\n"	\
	    : "=&r"(bit)				\
	    : "r"(x), "r"(32)				\
	    : "icc0", "cc4"				\
	    );						\
							\
	bit;						\
})

/**
 * fls64 - find last bit set in a 64-bit value
 * @n: the value to search
 *
 * This is defined the same way as ffs:
 * - return 64..1 to indicate bit 63..0 most significant bit set
 * - return 0 to indicate no bits set
 */
static inline __attribute__((const))
int fls64(u64 n)
{
	union {
		u64 ll;
		struct { u32 h, l; };
	} _;
	int bit, x, y;

_.ll = n;

asm("	subcc.p		%3,gr0,gr0,icc0		\n"
	    "	subcc		%4,gr0,gr0,icc1		\n"
	    "	ckne		icc0,cc4		\n"
	    "	ckne		icc1,cc5		\n"
	    "	norcr		cc4,cc5,cc6		\n"
	    "	csub.p		%0,%0,%0	,cc6,1	\n"
	    "	orcr		cc5,cc4,cc4		\n"
	    "	andcr		cc4,cc5,cc4		\n"
	    "	cscan.p		%3,gr0,%0	,cc4,0	\n"
	    "   setlos		#64,%1			\n"
	    "	cscan.p		%4,gr0,%0	,cc4,1	\n"
	    "   setlos		#32,%2			\n"
	    "	csub.p		%1,%0,%0	,cc4,0	\n"
	    "	csub		%2,%0,%0	,cc4,1	\n"
	    : "=&r"(bit), "=r"(x), "=r"(y)
	    : "0r"(_.h), "r"(_.l)
	    : "icc0", "icc1", "cc4", "cc5", "cc6"
	    );
	return bit;

}

/**
 * ffs - find first bit set
 * @x: the word to search
 *
 * - return 32..1 to indicate bit 31..0 most least significant bit set
 * - return 0 to indicate no bits set
 */
static inline __attribute__((const))
int ffs(int x)
{
	/* Note: (x & -x) gives us a mask that is the least significant
	 * (rightmost) 1-bit of the value in x.
	 */
	return fls(x & -x);
}

/**
 * __ffs - find first bit set
 * @x: the word to search
 *
 * - return 31..0 to indicate bit 31..0 most least significant bit set
 * - if no bits are set in x, the result is undefined
 */
static inline __attribute__((const))
int __ffs(unsigned long x)
{
	int bit;
	asm("scan %1,gr0,%0" : "=r"(bit) : "r"(x & -x));
	return 31 - bit;
}

/**
 * __fls - find last (most-significant) set bit in a long word
 * @word: the word to search
 *
 * Undefined if no set bit exists, so code should check against 0 first.
 */
static inline unsigned long __fls(unsigned long word)
{
	unsigned long bit;
	asm("scan %1,gr0,%0" : "=r"(bit) : "r"(word));
	return bit;
}

/*
 * special slimline version of fls() for calculating ilog2_u32()
 * - note: no protection against n == 0
 */
#define ARCH_HAS_ILOG2_U32
static inline __attribute__((const))
int __ilog2_u32(u32 n)
{
	int bit;
	asm("scan %1,gr0,%0" : "=r"(bit) : "r"(n));
	return 31 - bit;
}

/*
 * special slimline version of fls64() for calculating ilog2_u64()
 * - note: no protection against n == 0
 */
#define ARCH_HAS_ILOG2_U64
static inline __attribute__((const))
int __ilog2_u64(u64 n)
{
	union {
		u64 ll;
		struct { u32 h, l; };
	} _;
	int bit, x, y;

_.ll = n;

asm("	subcc		%3,gr0,gr0,icc0		\n"
	    "	ckeq		icc0,cc4		\n"
	    "	cscan.p		%3,gr0,%0	,cc4,0	\n"
	    "   setlos		#63,%1			\n"
	    "	cscan.p		%4,gr0,%0	,cc4,1	\n"
	    "   setlos		#31,%2			\n"
	    "	csub.p		%1,%0,%0	,cc4,0	\n"
	    "	csub		%2,%0,%0	,cc4,1	\n"
	    : "=&r"(bit), "=r"(x), "=r"(y)
	    : "0r"(_.h), "r"(_.l)
	    : "icc0", "cc4"
	    );
	return bit;
}

#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>

#include <asm-generic/bitops/le.h>

#include <asm-generic/bitops/ext2-atomic-setbit.h>

#endif /* __KERNEL__ */

#endif /* _ASM_BITOPS_H */